JPH0239118U - - Google Patents

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Publication number
JPH0239118U
JPH0239118U JP11765488U JP11765488U JPH0239118U JP H0239118 U JPH0239118 U JP H0239118U JP 11765488 U JP11765488 U JP 11765488U JP 11765488 U JP11765488 U JP 11765488U JP H0239118 U JPH0239118 U JP H0239118U
Authority
JP
Japan
Prior art keywords
signal
input terminal
input
signals
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11765488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11765488U priority Critical patent/JPH0239118U/ja
Publication of JPH0239118U publication Critical patent/JPH0239118U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示す図、第2図
は従来のS/D変換装置を示す図である。 図において1はスコツト・トランス、2はアナ
ログ・デイジタル変換器、3は象限選択回路、4
は余弦乗算器、5は正弦乗算器、6は引き算器、
7は選択器、8は加算器、9はレジスタ、10は
トランス、11は排他的論理和ゲート、12は位
相検波器、13は電圧制御発信器、14は可逆カ
ウンタ、15は符号反転器である。なお、各図中
同一符号は同一又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional S/D conversion device. In the figure, 1 is a Scott transformer, 2 is an analog-to-digital converter, 3 is a quadrant selection circuit, and 4 is a quadrant selection circuit.
is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter,
7 is a selector, 8 is an adder, 9 is a register, 10 is a transformer, 11 is an exclusive OR gate, 12 is a phase detector, 13 is a voltage controlled oscillator, 14 is a reversible counter, and 15 is a sign inverter. be. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3相のシンクロ信号を入力し、2相のレゾルバ
信号に変換するスコツト・トランス又は変換回路
と、入力端に前記スコツト・トランスの出力の2
相のレゾルバ信号の一方の正弦波の信号を入力し
、デイジタル信号に変換する第1のアナログ・デ
イジタル変換器と、入力端に前記スコツト・トラ
ンス出力の2相のレゾルバ信号の一方の余弦波の
信号を入力し、デイジタル信号に変換する第2の
アナログ・デイジタル変換器と、2つの入力端を
有し、その第1の入力端に前記第1のアナログ・
デイジタル変換器の出力信号を入力し、第2の入
力端に前記第2のアナログ・デイジタル変換器の
出力信号を入力し、角度の象限により2つの信号
を出力する象限選択回路と、2つの信号を入力し
第1の入力信号と第2の入力信号の余弦の値と掛
け算する余弦乗算器と、2つの信号を入力し、第
1の入力信号と第2の入力信号の正弦の値と掛け
算する正弦乗算器と、2つの信号を入力し2つの
信号を引き算する引き算器と、1つの信号を入力
しその符号を反転する符号反転器と2つの信号を
入力しその一方を選択出力する選択器と、2つの
信号を入力し2つの信号をたし算する加算器と、
2つの信号を入力し第1の入力信号により、第2
の入力信号を一時保持するレジスタと、2つの信
号の排他的論理和を出力する排他的論理和ゲート
により構成されたシンクロ・デイジタル変換装置
において、第1のに入力端に前記象限選択回路の
2つの出力信号の一方の正弦波を入力し、第2の
入力端に前記レジスタの信号を入力し、第2の入
力端に角度の余弦の値を第1の入力端の信号に掛
け算する余弦乗算器と、第1の入力端に前記象限
選択回路の2つの出力信号の一方の余限波を入力
し、第2の入力端に前記レジスタの信号を入力し
、第2の入力端の角度の正弦の値を第1の入力端
の信号に掛け算する正弦乗算器と、2つの入力端
の第1の入力端に前記余弦乗算器の出力信号を入
力し、第2の入力端に前記正弦乗算器の出力信号
を入力し、2つの信号を引き算する引き算器と、
入力端に前記引き算器の出力を入力し符号を反転
する符号反転器と、第1の入力端に前記レジスタ
の出力信号を入力し、第2の入力端に基準信号を
入力し、2つの信号の排他的論理和を出力する排
他的論理和ゲートと、3つの入力端の第1の入力
端に前記引き算器の出力信号を入力し、第2の入
力端に前記符号反転器の出力信号を入力し、第3
の入力端に前記排他的論理和ゲートの出力信号を
入力し、第3の入力端に与えられた信号により第
1の入力端に与えられた信号又第2の入力端に与
えられた信号を選び出力する選択器と、2つの入
力端の第1の入力端に前記レジスタの出力信号を
入力し、第2の入力端に前記選択器の出力信号を
入力し、2つの信号をたし算する加算器と、2つ
の入力端の第1の入力端にクロツク信号を入力し
、第2の入力端に前記加算器の出力信号を入力し
第1の入力端に与えられた信号で第2の入力端に
与えられた信号を一時保持するレジスタとを備え
たことを特徴とするシンクロ・デイジタル変換装
置。
A Scotto transformer or a conversion circuit that inputs a 3-phase synchro signal and converts it into a 2-phase resolver signal, and 2 outputs of the Scotto transformer at the input end.
A first analog-to-digital converter inputs a sine wave signal of one of the two-phase resolver signals and converts it into a digital signal; a second analog-to-digital converter for inputting a signal and converting it into a digital signal; and a second analog-to-digital converter for inputting a signal and converting it into a digital signal;
a quadrant selection circuit that inputs an output signal of a digital converter, inputs an output signal of the second analog-to-digital converter to a second input terminal, and outputs two signals according to an angular quadrant; a cosine multiplier that receives two signals and multiplies them by the cosine values of the first and second input signals; and a cosine multiplier that receives two signals and multiplies them by the sine values of the first and second input signals A sine multiplier that inputs two signals and subtracts the two signals, a sign inverter that inputs one signal and inverts its sign, and a selection that inputs two signals and selects and outputs one of them. an adder that inputs two signals and adds the two signals;
When two signals are input, the first input signal causes the second
In the synchro-digital conversion device, the synchro-digital conversion device is constituted by a register that temporarily holds an input signal of two signals, and an exclusive OR gate that outputs an exclusive OR of two signals. Cosine multiplication that inputs one sine wave of two output signals, inputs the signal of the register to the second input terminal, and multiplies the signal at the first input terminal by the value of the cosine of the angle at the second input terminal. input the residual wave of one of the two output signals of the quadrant selection circuit to the first input terminal, input the signal of the register to the second input terminal, and calculate the sine of the angle at the second input terminal. a sine multiplier that multiplies a value by a signal at a first input terminal; a first input terminal of the two input terminals receives the output signal of the cosine multiplier; and a second input terminal receives the output signal of the sine multiplier; a subtracter that inputs an output signal and subtracts the two signals;
a sign inverter that inputs the output of the subtracter to an input terminal and inverts the sign; a sign inverter that inputs the output signal of the register to a first input terminal, and a reference signal to a second input terminal; an exclusive OR gate that outputs the exclusive OR of the subtracter, the output signal of the subtracter is input to the first input terminal of the three input terminals, and the output signal of the sign inverter is input to the second input terminal. Enter the third
The output signal of the exclusive OR gate is input to the input terminal of , and the signal applied to the first input terminal or the signal applied to the second input terminal is controlled by the signal applied to the third input terminal. The output signal of the register is input to the first input terminal of the selector for selecting and outputting, and the output signal of the selector is input to the second input terminal, and the two signals are added. a clock signal is input to the first input terminal of the two input terminals, an output signal of the adder is input to the second input terminal, and the second 1. A synchro-digital conversion device comprising: a register for temporarily holding a signal applied to an input terminal of the synchro-digital converter.
JP11765488U 1988-09-07 1988-09-07 Pending JPH0239118U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11765488U JPH0239118U (en) 1988-09-07 1988-09-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11765488U JPH0239118U (en) 1988-09-07 1988-09-07

Publications (1)

Publication Number Publication Date
JPH0239118U true JPH0239118U (en) 1990-03-15

Family

ID=31361300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11765488U Pending JPH0239118U (en) 1988-09-07 1988-09-07

Country Status (1)

Country Link
JP (1) JPH0239118U (en)

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