JPH0161614U - - Google Patents
Info
- Publication number
- JPH0161614U JPH0161614U JP15715487U JP15715487U JPH0161614U JP H0161614 U JPH0161614 U JP H0161614U JP 15715487 U JP15715487 U JP 15715487U JP 15715487 U JP15715487 U JP 15715487U JP H0161614 U JPH0161614 U JP H0161614U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input terminal
- digital
- inputs
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 1
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
Description
第1図はこの考案の一実施例を示す図、第2図
は従来のS/D変換装置を示す図である。
図において1は象限選択回路、2は余弦乗算器
、3は正弦乗算器、4は引き算器、5はアナログ
・デイジタル変換器、6は符号反転器、7は加算
器、8はレジスタ、9は符号判定器、10はスコ
ツト・トランス、11はトランス、12は位相検
波器、13は電圧制御発振器、14は可逆カウン
タ、15は選択器である。なお、各図中同一符号
は同一、又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional S/D conversion device. In the figure, 1 is a quadrant selection circuit, 2 is a cosine multiplier, 3 is a sine multiplier, 4 is a subtracter, 5 is an analog-to-digital converter, 6 is a sign inverter, 7 is an adder, 8 is a register, and 9 is a 10 is a Scott transformer, 11 is a transformer, 12 is a phase detector, 13 is a voltage controlled oscillator, 14 is a reversible counter, and 15 is a selector. Note that the same reference numerals in each figure indicate the same or equivalent parts.
Claims (1)
号に変換するスコツト・トランスと、アナログの
信号とデイジタルの角度信号を入力し、デイジタ
ルの角度の正弦の値をアナログ信号に掛け算する
正弦乗算器と、アナログの信号とデイジタルの角
度信号を入力し、デイジタルの角度の余弦の値を
アナログ信号に掛け算する余弦乗算器と、2つの
信号を引き算する引き算器と、アナログの信号を
入力しデイジタルの信号に変換するアナログ・デ
イジタル変換器と、デイジタルの信号を入力しそ
の符号を反転する符号反転器と、2つのデイジタ
ル信号を入力しその一方を選択出力する選択器と
、2つの信号を加え合わせる加算器と、デイジタ
ル値を一時保持するレジスタとアナログの信号を
入力しその符号を判定する符号判定器とを備えた
トラツキング型シンクロ・デイジタル変換器にお
いて、第1の入力端に前記スコツト・トランスの
2つの出力信号の一方の正弦波の信号を入力し、
第2の入力端に前記レジスタのデイジタル信号を
入力しデイジタル信号の角度の余弦の値を正弦波
の信号に掛け算する余弦乗算器と、第1の入力端
に前記スコツト・トランスの2つの出力信号の一
方の正弦波の信号を入力し、第2の入力端に前記
レジスタのデイジタル信号を入力しデイジタル信
号の角度の正弦の値を余弦波の信号に掛け算する
正弦乗算器と、第1の入力端に前記余弦乗算器の
出力を入力し、第2の入力端に前記正弦乗算器の
出力を入力し、2つの信号を引き算する引き算器
と、入力端に前記引き算器の出力を入力し、デイ
ジタル信号に変換するアナログ・デイジタル変換
器と、入力端に基準信号を入力し、その符号を判
定する符号判定器と、入力端に前記アナログ・デ
イジタル変換器の出力を入力し符号を反転する符
号反転器を、第1の入力端に前記アナログ・デイ
ジタル変換器の出力を入力し、第2の入力端に前
記符号反転器の出力を入力し、第3の入力端に前
記符号判定器の出力を入力し、第3の入力端に与
えられた信号により第1の入力端に与えられた信
号又は第2の入力端に与えられた信号を選び出力
する選択器と、第1の入力端に前記選択器の出力
を入力し、第2の入力端に後述のレジスタのデイ
ジタル信号を入力し加え合わせる加算器と、第1
の入力端にクロツクを入力し、第2の入力端に上
記加算器の出力を入力し第1の入力端に与えられ
た信号で第2の入力端に与えられた信号を一時保
持するレジスタとを備えたことを特徴とするシン
クロ・デイジタル変換装置。 A Scotto transformer inputs a three-phase synchronized signal and converts it into a two-phase resolver signal, and a sine multiplier inputs an analog signal and a digital angle signal and multiplies the analog signal by the sine value of the digital angle. , a cosine multiplier that inputs an analog signal and a digital angle signal and multiplies the analog signal by the cosine value of the digital angle, a subtracter that subtracts the two signals, and a cosine multiplier that inputs an analog signal and multiplies the digital signal. an analog-to-digital converter that converts into , a sign inverter that inputs a digital signal and inverts its sign, a selector that inputs two digital signals and selects and outputs one of them, and an adder that adds the two signals together. A tracking type synchro-digital converter is equipped with a register for temporarily holding a digital value, and a sign determiner for inputting an analog signal and determining its sign. Input one sine wave signal of two output signals,
A cosine multiplier that inputs the digital signal of the register to a second input terminal and multiplies the sine wave signal by the value of the cosine of the angle of the digital signal, and a first input terminal that receives the two output signals of the Scott transformer. a sine multiplier that inputs one sine wave signal of the register, inputs the digital signal of the register to a second input terminal, and multiplies the cosine wave signal by the sine value of the angle of the digital signal; inputting the output of the cosine multiplier at one end, inputting the output of the sine multiplier at a second input end, a subtracter for subtracting two signals, and inputting the output of the subtracter at the input end, an analog-to-digital converter for converting into a digital signal; a sign determiner for inputting a reference signal into an input terminal and determining its sign; and a sign determining device for inputting the output of the analog-to-digital converter at an input terminal and inverting the sign. The output of the analog-to-digital converter is input to the first input terminal of the inverter, the output of the sign inverter is input to the second input terminal, and the output of the sign determiner is input to the third input terminal of the inverter. a selector that selects and outputs the signal given to the first input terminal or the signal given to the second input terminal according to the signal given to the third input terminal; an adder that inputs the output of the selector and inputs and adds a digital signal of a register to be described later to a second input terminal;
A register that inputs a clock to the input terminal of the register, inputs the output of the adder to the second input terminal, and temporarily holds the signal given to the second input terminal with the signal given to the first input terminal. A synchro digital conversion device characterized by comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15715487U JPH0161614U (en) | 1987-10-14 | 1987-10-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15715487U JPH0161614U (en) | 1987-10-14 | 1987-10-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0161614U true JPH0161614U (en) | 1989-04-19 |
Family
ID=31436350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15715487U Pending JPH0161614U (en) | 1987-10-14 | 1987-10-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0161614U (en) |
-
1987
- 1987-10-14 JP JP15715487U patent/JPH0161614U/ja active Pending