JPH0189318U - - Google Patents

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Publication number
JPH0189318U
JPH0189318U JP18473087U JP18473087U JPH0189318U JP H0189318 U JPH0189318 U JP H0189318U JP 18473087 U JP18473087 U JP 18473087U JP 18473087 U JP18473087 U JP 18473087U JP H0189318 U JPH0189318 U JP H0189318U
Authority
JP
Japan
Prior art keywords
signal
input
input terminal
inputs
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18473087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18473087U priority Critical patent/JPH0189318U/ja
Publication of JPH0189318U publication Critical patent/JPH0189318U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す図、第2図
は従来のR/D変換装置を示す図である。 図において、2はアナログ・デイジタル変換器
、4は余弦乗算器、5は正弦乗算器、6は引き算
器、7は選択器、8は加算器、9はレジスタ、1
1は符号判定器、12は位相検波器、13は電圧
制御発信器、14は可逆カウンタ、15は符号反
転器である。なお、各図中同一符号は同一又は相
当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional R/D conversion device. In the figure, 2 is an analog-digital converter, 4 is a cosine multiplier, 5 is a sine multiplier, 6 is a subtracter, 7 is a selector, 8 is an adder, 9 is a register, 1
1 is a sign determiner, 12 is a phase detector, 13 is a voltage controlled oscillator, 14 is a reversible counter, and 15 is a sign inverter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端に2相のレゾルバ信号の一方の正弦波の
信号を入力し、デイジタル信号に変換する第1の
アナログ・デイジタル変換器と、入力端に2相の
レゾルバ信号の一方の余弦波の信号を入力し、デ
イジタル信号に変換する第2のアナログ・デイジ
タル変換器と、2つの信号を入力し第1の入力信
号と第2の入力信号の余弦の値と掛け算する余弦
乗算器と、2つの信号を入力し第1の入力信号と
第2の入力信号の正弦の値と掛け算する正弦乗算
器と、2つの信号を入力し2つの信号を引き算す
る引き算器と、1つの信号を入力しその符号を反
転する符号反転器と、2つの信号を入力しその一
方を選択出力する選択器と、2つの信号を入力し
、2つの信号をたし算する加算器と、2つの信号
を入力し第1の入力信号により、第2の入力信号
を一時保持するレジスタと、入力信号の符号を判
定する符号判定器により構成されたレゾルバ・デ
イジタル変換装置において、第1の入力端に前記
第1のアナログ・デイジタル変換器の出力信号を
入力し、第2の入力端の角度の余弦の値を第1の
入力端の信号に掛け算する余弦乗算器と、第1の
入力端に前記第2のアナログ・デイジタル変換器
の出力信号を入力し、第2の入力端に前記レジス
タの信号を入力し、第2の入力端の角度の正弦の
値を第1の入力端の信号に掛け算する正弦乗算器
と、2つの入力端の第1の入力端に前記余弦乗算
器の出力信号を入力し、第2の入力端に前記正弦
乗算器の出力信号を入力し、2つの信号を引き算
する引き算器と、入力端に前記引き算器の出力を
入力し符号を反転する符号反転器と、入力端に基
準信号を入力しその符号を判定する符号判定器と
、3つの入力端の第1の入力端に前記引き算器の
出力信号を入力し、第2の入力端に前記符号反転
器の出力信号を入力し、第3の入力端に前記符号
判定器の出力信号を入力し、第3の入力端に与え
られた信号により第1の入力端に与えられた信号
又は第2の入力端に与えられた信号を選らび出力
する選択器と、2つの入力端の第1の入力端に前
記レジスタの出力信号を入力し、第2の入力端に
前記選択器の出力信号を入力し、2つの信号をた
し算する加算器と、2つの入力端の第1の入力端
にクロツク信号を入力し、第2の入力端に前記加
算器の出力信号を入力し第1の入力端に与えられ
た信号で第2の入力端に与えられた信号を一時保
持するレジスタとを備えたことを特徴とするレゾ
ルバ・デイジタル変換装置。
A first analog-to-digital converter inputs a sine wave signal of one of the two-phase resolver signals at the input end and converts it into a digital signal, and a cosine wave signal of one of the two-phase resolver signals is input to the input end. a second analog-to-digital converter that receives the input signal and converts it into a digital signal; a cosine multiplier that receives the two signals and multiplies them by the cosine values of the first input signal and the second input signal; A sine multiplier that inputs and multiplies the sine value of the first input signal and a second input signal, a subtracter that inputs two signals and subtracts the two signals, and a subtracter that inputs one signal and multiplies its sign. a selector that inputs two signals and selects and outputs one of them; an adder that inputs two signals and adds the two signals; and a selector that inputs two signals and adds the two signals. In a resolver/digital converter, the device includes a register that temporarily holds a second input signal in response to a first input signal, and a sign determiner that determines the sign of the input signal. - A cosine multiplier that inputs the output signal of the digital converter and multiplies the value of the cosine of the angle at the second input terminal by the signal at the first input terminal; a sine multiplier that inputs the output signal of the digital converter, inputs the signal of the register to a second input terminal, and multiplies the signal of the first input terminal by the value of the sine of the angle at the second input terminal; , a subtracter that inputs the output signal of the cosine multiplier to a first input terminal of two input terminals, inputs the output signal of the sine multiplier to a second input terminal, and subtracts the two signals; a sign inverter that inputs the output of the subtracter to an input terminal and inverts the sign; a sign determiner that inputs a reference signal to the input terminal and determines the sign; and a first input terminal of the three input terminals The output signal of the subtracter is inputted, the output signal of the sign inverter is inputted to the second input terminal, the output signal of the sign determiner is inputted to the third input terminal, and the signal is applied to the third input terminal. a selector that selects and outputs the signal applied to the first input terminal or the signal applied to the second input terminal according to the input signal; and the output signal of the register is input to the first input terminal of the two input terminals. is input, the output signal of the selector is input to the second input terminal, an adder adds the two signals, a clock signal is input to the first input terminal of the two input terminals, and the output signal of the selector is input to the second input terminal. and a register that inputs the output signal of the adder to the second input terminal and temporarily holds the signal given to the second input terminal with the signal given to the first input terminal.・Digital conversion device.
JP18473087U 1987-12-03 1987-12-03 Pending JPH0189318U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18473087U JPH0189318U (en) 1987-12-03 1987-12-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18473087U JPH0189318U (en) 1987-12-03 1987-12-03

Publications (1)

Publication Number Publication Date
JPH0189318U true JPH0189318U (en) 1989-06-13

Family

ID=31476071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18473087U Pending JPH0189318U (en) 1987-12-03 1987-12-03

Country Status (1)

Country Link
JP (1) JPH0189318U (en)

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