JPH01105811U

JPH01105811U -

Info

Publication number: JPH01105811U
Application number: JP181188U
Authority: JP
Priority date: 1988-01-11
Filing date: 1988-01-11
Publication date: 1989-07-17

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す図、第２図
は従来のＲ／Ｄ変換装置を示す図、第３図は基準
信号が０の場合レゾルバ信号とデイジタル値が０
〜９０度の範囲の記憶器のデータを示す図、第４
図は基準信号が１の場合レゾルバ信号とデイジタ
ル値が０〜９０度の範囲の記憶器のデータを示す
図である。図において、２はアナログ・デイジタル変換器
、４は記憶器、６は符号判定器、７は加算器、８
はレジスタ、９は余弦乗算器、１０は正弦乗算器
、１１は引き算器、１２は位相検波器、１３は電
圧制御発振器、１４は可逆カウンタである。なお
、各図中同一符号は同一又は相当部分を示す。 Fig. 1 shows an embodiment of this invention, Fig. 2 shows a conventional R/D converter, and Fig. 3 shows that when the reference signal is 0, the resolver signal and digital value are 0.
4th diagram showing data of the memory device in the range of ~90 degrees
The figure shows the resolver signal and the data in the memory in the range of digital values from 0 to 90 degrees when the reference signal is 1. In the figure, 2 is an analog-to-digital converter, 4 is a memory, 6 is a sign determiner, 7 is an adder, and 8
9 is a register, 9 is a cosine multiplier, 10 is a sine multiplier, 11 is a subtracter, 12 is a phase detector, 13 is a voltage controlled oscillator, and 14 is a reversible counter. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

A first analog-to-digital converter inputs a sine wave signal of one of the two-phase resolver signals at the input end and converts it into a digital signal, and a cosine wave signal of one of the two-phase resolver signals is input to the input end. a second analog-to-digital converter that inputs the input signal and converts it into a digital signal; a sign determiner that inputs the reference signal to the input terminal and determines its sign; inputs the address signal and outputs the data specified by the address. an adder that inputs two signals and outputs the sum of the two signals, and a register that inputs the two signals and temporarily holds the second input signal according to the first input signal, In the resolver-digital converter, the output signal of the first analog-to-digital converter is input to the first input terminal of four input terminals, and the output signal of the first analog-to-digital converter is input to the second input terminal.
Input the output signal of the digital converter, input the signal of the register to the third input terminal, input the signal of the sign determiner to the fourth input terminal, and output the stored data according to the four input signals. Memory device and 2
an adder that inputs the output signal of the storage device to a first input terminal of two input terminals, inputs the output signal of the register to a second input terminal, and adds the two signals;
A clock signal is input to the first input terminal of the two input terminals, the output signal of the adder is input to the second input terminal, and the signal applied to the first input terminal is applied to the second input terminal. What is claimed is: 1. A resolver/digital conversion device comprising: a register for temporarily holding a received signal;