JPH03261820A - Digital r/d converter - Google Patents

Abstract

PURPOSE:To remarkably simplify the assembly work and to improve the reliability by composing all the circuit systems except an A/D converter of digital circuits in the structure of a gate array. CONSTITUTION:A synchronous signal 1a is converted to resolver signals 1b, 1c by a Scott transformer 1. The signals 1b, 1c are digitalized by A/D converters 10, 11 and fed to a quadrant selection circuit 2. A first output A obtained in the circuit 2 is compared at 12 with a second output B which is obtained at 13 by multiplying the first output A with cos theta. As a result, an up pulse 14a is input to a counter 15 from a first gate 14. When A=B, generation of a pulse is stopped. If A<B, a down pulse 16a is input from a second gate 16 to the counter 15. Therefore, the operation of the circuit systems proceeds until the outputs A, B are agreed at the comparator 12. When generation of a pulse is stopped, theta becomes equal to phi thereby obtaining a digital output phi, i.e., an output phi. The other circuit systems than the A/D converters are constituted of digital circuits into the structure of a gate array.

Description

DETAILED DESCRIPTION OF THE INVENTION a. Industrial Application Field The present invention relates to a digital R/D converter, and in particular to an A/D converter.
The present invention relates to a novel improvement for realizing cost reduction by configuring all circuit systems other than the D converter with digital circuits, for example, by forming them into an array.

b. Conventional technology This type of R/D variation that has been used in the past #! ! ! ! There are many types of vessels, but to describe a typical configuration, we can cite the configuration shown in Figure 2, which was manufactured in-house by the applicant.

That is, what is indicated by the reference numeral 1 in FIG. 2 is a SCOTT transformer, and a first input terminal S provided on the input side of this SCOTT transformer 1.

The synchro signal 1a is input to the second input terminal S2 and the third input terminal S, and the resolver signals 1b and lc obtained from the first output terminal S4 and the second output terminal S of the scooter 1 to the lance 1 is input to the quadrant selection circuit 2.

The reference transformer IA provided in the Scott transformer 1 is provided with input terminals R, , R, for inputting the reference input signal 1d, and the output terminal R1 of the reference transformer 1A is A reference signal REF is output.

The first output A of the sine wave and the second output B of the eO8 wave obtained from the quadrant selection circuit I#I2 are the first output A of the sine wave and the second output B of the eO8 wave obtained from the quadrant selection circuit I#I2. 2nd D/A
It is input to the converter 3.4 and multiplied by eO8φ and sinφ, and the first output 3a of the first D/A converter 3 and the second
A second output 4a of the D/A converter 4 is input to an adder/subtractor 5.

The output signal 5a from the adder/subtracter 5 is input to the VC via the wI rectifier 6 to which the reference signal REF is input.
A pulse output a from the oscillator 7 is input to a counter 8.

The conventional R/D converter is configured as described above, and its operation will be explained below.

First, synchro signal 1 input to Scotto transformer 1
a is converted into a resolver signal 1b and sent to the first D/A as the first output A and second output B via the quadrant selection circuit 2.
The signal is input to a converter 3 and a second D/A converter 4.

In each D/A converter 3.4, V, sinω1sinθX cos
φ and Vl sin ωt-cos θX sin φ are calculated, and a first output 3a and a second output 4a are output.

Each of these outputs 3a, 4a is outputted by an adder/subtractor 5 to V2si
nω sinθX cosφ−V sinωt −co
sθX sinφ−V2sinωtxsin(θ−φ)
By synchronous rectification with the reference signal REF, sinωt becomes a DC component, and ■, 5in
(θ-φ> output signal 6a is input to the oscillator 7.

The oscillator 7 generates pulses until the aforementioned V, 5 in (θ-φ)-0, that is, θ=φ, and the entire system performs a tracking operation.

C1 Problems to be Solved by the Invention Since the conventional R/D converter has an elliptical structure as described above, it has had the following problems.

In other words, of the entire circuit configuration, except for Karan and Ri,
Since all of the circuits are analog circuits, the circuit configuration must be discrete or hybrid, and although it is possible to achieve high accuracy, it has been impossible to reduce costs.

In addition, since they are discrete or hybrid, the assembly of the circuit configuration is complicated, making it impossible to simplify wiring connections, etc., and there are also problems in terms of reliability.

The present invention was made to solve the above-mentioned problems.In particular, all circuit systems other than the A/D converter are constructed with digital circuits, and costs are reduced by forming a gate array. An object of the present invention is to provide a digital R/D converter that can perform the following functions.

41 Means for Solving the Problems The digital R/D converter according to the present invention includes a first transformer for converting a synchro signal into a resolver signal, and a first transformer for converting the resolver signal from analog to digital. A second A/D converter, a quadrant selection circuit into which output signals from each A/D converter are input, and a first output (A) of s i ++θ obtained from the quadrant selection circuit.
, a third output (b) consisting of cos θ and tanφ outputted from the quadrant selection circuit through a multiplier, the first output (A) and the third output ([3
), and a counter to which an up pulse or a down pulse is input depending on the magnitude of the first output (A) and the third output (B).

In the digital R/D converter according to the present invention, the resolver signal is digitized by the A/D converter that receives the resolver signal, and the sin θ which has passed through the quadrant selection circuit is directly input to the comparator, and the cos θ is input to the comparator as e03θX tanφ by multiplication of tanφ.

In this comparator, this sinθ and cosθX tan
φ are compared, an up pulse is generated when sin θ > eos θ cos θX tan φ, and the above equation holds true when θ-φ, and a digital output φ is obtained.

Further, since all the circuit configurations other than the A/D converter are digital, the circuit configuration can be a gate array, and the circuit configuration and assembly can be greatly simplified.

f. Embodiments Hereinafter, preferred embodiments of the digital R/D converter according to the present invention will be described in detail with reference to the drawings.

It should be noted that the same or equivalent parts as in the conventional example will be described with the same reference numerals.

FIG. 1 is a block diagram showing a digital R/D converter according to the present invention.

In the figure, the reference numeral 1 is a Scotto lance, and the first input terminal S1, second input terminal S2, and third input terminal S3 provided on the input side of the Scotto 1 to Lance 1 are synchronized. When signal 1a is input, this tip)
- the first output terminal S4 and the second output terminal S of the transformer 1;
5 Resolver signals obtained from 1. b, lc are input to the quadrant selection circuit 2 after being digitized via A/D converters 10.11.

The reference transformer 1A provided in the Scott transformer 1 is provided with input terminals R, , R2 for inputting the reference input signal 1d, and the output terminal n3 of the reference transformer IA is provided with a reference input signal 1d. A signal REF is output.

The first output A of sin θ obtained from the quadrant selection circuit 2
is directly input to the comparator 12, and the quadrant selection time! The second output B of eO9θ from B2 is multiplied by tanφ in the multiplier 13 and then inputted to the comparator 12 as eO3θ·tanφ.

A first output 12a from the comparator 12 is connected to a first gate 14.
The second output 12b from the comparator 12 is input to the counter 15 via the second gate 16.
5 is entered.

The output φ outputted from the counter 15 is supplied to the multiplication unit 13 and the quadrant selection circuit 2, and the timing signal 17a from the timing circuit 17 to which the reference signal REF is supplied is supplied to the A/D conversion circuit 2. 11 and each gate 14.16.

The digital R/D converter according to the present invention is configured as described above, and its operation will be explained below.

First, the synchronized signal 1a is converted into resolver signals 1b and 1c by a Scott transformer 1, and these resolver signals 1b and lc are digitized by each A/D converter 1°11 and supplied to the quadrant selection circuit 2. Ru.

The first output A of sin θ obtained from this quadrant selection circuit 2
and cos θ are multiplied by the multiplication unit 13, resulting in two outputs B.
is compared in the comparator 12, and in this comparator 12, A
>B, that is, sin θ>cos θX, tan ψ, the up pulse 14m from the first gate 14 is
is input.

Also, A=Bz, that is, sinθ=cosθX tanφ
In the case of , the pulse stops and A<B, that is, sin
When θ<cosθX tanφ, the down pulse 16a is input to the counter 15 from the second gate 16.

Therefore, the operation of the circuit system slows down until the first output A and the second output B of the comparator 12 match, and the pulse stops, that is, sin θ=cos θX Lan digital output φ, that is, output φ is obtained.

Therefore, the above-mentioned quadrant selection circuit 2, multiplication section 13, comparator 1
2. The gates 14 and 16, the counter 15 and the timing circuit 17 can all be implemented as digital circuits, for example, in the form of a one-chip gate array to improve assembly and reliability. be able to.

g1 Effects of the Invention Since the digital R/D converter according to the invention is f# controlled as described above, the following effects can be obtained.

In other words, all circuit configurations other than the A/D converter can be digitized, so unlike conventional discrete or hybrid analog circuits, for example,
By forming a gate array, assembly can be greatly simplified and reliability can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital R/D converter according to the present invention, and FIG. 2 is a block diagram showing a conventional R/D converter. 1 is a Scott transformer, 1a is a synchro signal, 1b, 1
c is the resolver signal, 2 is the quadrant selection circuit, A is the first output,
B is the second output, 10 is the first A/D converter, 11 is the second
12 is a comparator, 13 is a multiplication unit, 14a is an up pulse, 15 is a counter, and 16a is a down pulse. Figure (1) LII Scotto transformer (10) receives synchro signals (Ib, 1c)1. t Reso LAG issue (2) is elephant 1
! J! The selection circuit (A) is the first output (B) +2, the second output (10) is the first A/D converter (11), the second A/D converter (+2), and the U comparator (13) is the multiplication unit (14a). )I! Up pulse (+5) lma Kajunta (16 o) Lt' down pulse

Claims (1)

[Claims] A Scott transformer (1) for converting a synchronized signal (1a) into a resolver signal (1b, 1c), and first and second A/D converters for converting the resolver signal (1b, 1c) from analog to digital. (10, 11), a quadrant selection circuit (2) into which the output signals from each A/D converter (10, 11) are input, and a first output of sin θ obtained from the quadrant selection circuit (2). (A) and a second output consisting of cos θ and tanφ outputted via the multiplication unit (13) by cos θ obtained from the quadrant selection circuit (2).
B), a comparator (12) to which the first output (A) and the third output (B) are input, and a comparator (12) that receives the first output (A) and the second output (B);
A counter (15) to which an up pulse (14a) or a down pulse (16a) is input depending on the magnitude of the output (B), the quadrant selection circuit (2), a comparator (12), a multiplication unit (13) and A digital R/D converter characterized in that a counter (15) is constructed from a digital circuit.