JPH0360018U - - Google Patents

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Publication number
JPH0360018U
JPH0360018U JP11988189U JP11988189U JPH0360018U JP H0360018 U JPH0360018 U JP H0360018U JP 11988189 U JP11988189 U JP 11988189U JP 11988189 U JP11988189 U JP 11988189U JP H0360018 U JPH0360018 U JP H0360018U
Authority
JP
Japan
Prior art keywords
signal
input terminal
input
inputs
reversible counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11988189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11988189U priority Critical patent/JPH0360018U/ja
Publication of JPH0360018U publication Critical patent/JPH0360018U/ja
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第4図はこの考案の一実施例を示す図
、第5図は従来のアナログ・デジタル変換装置を
示す図である。 図において、1……スコツト・トランス、2……
象限選択器、3……余弦乗算器、4……正弦乗算
器、5……引き算器、6……位相検波器、7……
電圧制御発振器、8……第1の可逆カウンタ、9
……第2の可逆カウンタ、10……タイマーであ
る。なお各図中同一符号は同一または相当部分を
示す。
1 to 4 are diagrams showing an embodiment of this invention, and FIG. 5 is a diagram showing a conventional analog-to-digital converter. In the figure, 1...Scotto transformer, 2...
Quadrant selector, 3... Cosine multiplier, 4... Sine multiplier, 5... Subtractor, 6... Phase detector, 7...
Voltage controlled oscillator, 8...first reversible counter, 9
. . . second reversible counter, 10 . . . timer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】 (1) 2つの入力端の第1の入力端にレゾルバ信
号の正弦波の信号を入力し第2の入力端に第1の
可逆カウンタの出力信号を入力し上記第1の可逆
カウンタの余弦値を第1の入力端の信号に掛け算
する余弦乗算器と、2つの入力端の第1の入力端
にレゾルバ信号の余弦波の信号を入力し第2の入
力端に上記第1の可逆カウンタの出力信号を入力
し、上記第1の可逆カウンタの正弦値を第1の入
力端の信号に掛け算する正弦乗算器と、上記余弦
乗算器と上記正弦乗算器の出力信号を入力し2つ
の信号の差を出力する引き算器と、2つの入力端
の第1の入力端に上記引き算器の出力信号を入力
し第2の入力端に搬送波を入力し第1の入力端の
信号を第2の入力端の信号で検波、整流する位相
検波器と、上記位相検波器の出力信号を入力して
入力信号により発振周波数が変化する電圧制御発
振器と、2つの入力端の第1の入力端に上記位相
検波器の出力信号を入力し第2の入力端に上記電
圧制御発振器のクロツク信号を入力し上昇または
下降のカウントをする上記第1の可逆カウンタと
、時間を計測するタイマーと、3つの入力端の第
1の入力端に上記位相検波器の出力信号を入力し
第2の入力端に上記電圧制御発振器のクロツク信
号を入力し第3の入力端に上記タイマーの信号を
入力し上昇または下降のカウントする第2の可逆
カウンタとを備えたことを特徴とするアナログ・
デジタル変換装置。 (2) レゾルバ信号の正弦波と余弦波の信号を入
力し象限選択された正弦波と余弦波の信号を出力
する象限選択器と、2つの入力端の第1の入力端
に上記象限選択器の正弦波の信号を入力し第2の
入力端に第1の可逆カウンタの出力信号を入力し
上記第1の可逆カウンタの余弦値を第1の入力端
の信号に掛け算する余弦乗算器と、2つの入力端
の第1の入力端に上記象限選択器の余弦波の信号
を入力し第2の入力端に上記第1の可逆カウンタ
の出力信号を入力し、上記第1の可逆カウンタの
正弦値を第1の入力端の信号に掛け算する正弦乗
算器と、上記余弦乗算器と上記正弦乗算器の出力
信号を入力し2つの信号の差を出力する引き算器
と、2つの入力端の第1の入力端に上記引き算器
の出力信号を入力し第2の入力端に搬送波を入力
し第1の入力端の信号を第2の入力端の信号で検
波、整流する位相検波器と、上記位相検波器の出
力信号を入力し入力信号により発振周波数が変化
する電圧制御発振器と、2つの入力端の第1の入
力端に上記位相検波器の出力信号を入力し第2の
入力端に上記電圧制御発振器のクロツク信号を入
力し上昇または下降のカウントをする上記第1の
可逆カウンタと、時間を計測するタイマーと、3
つの入力端の第1の入力端に上記位相検波器の出
力信号を入力し第2の入力端に上記電圧制御発振
器のクロツク信号を入力し第3の入力端に上記タ
イマーの信号を入力し上昇または下降のカウンタ
する第2の可逆カウンタとを備えたことを特徴と
するアナログ・デジタル変換装置。 (3) 3相のシンクロ信号を入力し2相のレゾル
バ信号に変換しりスコツト・トランスと、2つの
入力端の第1の入力端に上記スコツト・トランス
の出力レゾルバ信号の正弦波の信号を入力し第2
の入力端に第1の可逆カウンタの出力信号を入力
し上記第1の可逆カウンタの余弦値を第1の入力
端の信号に掛け算する余弦乗算器と、2つの入力
端の第1の入力端に上記スコツト・トランスの出
力レゾルバ信号の余弦波の信号を入力し第2の入
力端に上記第1の可逆カウンタの出力信号を入力
し、上記第1の可逆カウンタの正弦値を第1の入
力端の信号に掛け算する正弦乗算器と、上記余弦
乗算器と上記正弦乗算器の出力信号を入力し2つ
の信号の差を出力する引き算器と、2つの入力端
の第1の入力端に上記引き算器の出力信号を入力
し第2の入力端に搬送波を入力し第1の入力端の
信号を第2の入力端の信号で検波、整流する位相
検波器と、上記位相検波器の出力信号を入力し入
力信号により発振周波数が変化する電圧制御発振
器と、2つの入力端の第1の入力端に上記位相検
波器の出力信号を入力し第2の入力端に上記電圧
制御発振器のクロツク信号を入力し上昇または下
降のカウントをする上記第1の可逆カウンタと、
時間を計測するタイマーと、3つの入力端の第1
の入力端に上記位相検波器の出力信号を入力し第
2の入力端に上記電圧制御発振器のクロツク信号
を入力し第3の入力端に上記タイマーの信号を入
力し上昇または下降のカウントする第2の可逆カ
ウンタとを備えたことを特徴とするアナログ・デ
ジタル変換装置。 (4) 3相のシンクロ信号を入力し2相のレゾル
バ信号を出力するスコツト・トランスと、上記ス
コツト・トランスの出力するレゾルバ信号の正弦
波と余弦波の信号を入力し象限選択された正弦波
と余弦波の信号を出力する象限選択器と、2つの
入力端の第1の入力端に上記象限選択器の正弦波
の信号を入力し第2の入力端に第1の可逆カウン
タの出力信号を入力し上記可逆カウンタの余弦値
を第1の入力端の信号に掛け算する余弦乗算器と
、2つの入力端の第1の入力端に上記象限選択器
の余弦波の信号を入力し第2の入力端に上記第1
の可逆カウンタの出力信号を入力し、上記第1の
可逆カウンタの正弦値を第1の入力端の信号に掛
け算する正弦乗算器と、上記余弦乗算器と上記正
弦乗算器の出力信号を入力し2つの信号の差を出
力する引き算器と、2つの入力端の第1の入力端
に上記引き算器の出力信号を入力し第2の入力端
に搬送波を入力し第1の入力端の信号を第2の入
力端の信号で検波、整流する位相検波器と、上記
位相検波器の出力信号を入力し入力信号により発
振周波数が変化する電圧制御発振器と、2つの入
力端の第1の入力端に上記位相検波器の出力信号
を入力し第2の入力端に上記電圧制御発振器のク
ロツク信号を入力し上昇または下降のカウントを
する上記第1の可逆カウンタと、時間を計測する
タイマーと、3つの入力端の第1の入力端に上記
位相検波器の出力信号を入力し第2の入力端に上
記電圧制御発振器のクロツク信号を入力し第3の
入力端に上記タイマーの信号を入力し上昇または
下降のカウントする第2の可逆カウンタとを備え
たことを特徴とするアナログ・デジタル変換装置
[Claims for Utility Model Registration] (1) A sine wave signal of a resolver signal is inputted to the first input terminal of the two input terminals, and an output signal of the first reversible counter is inputted to the second input terminal, and the above a cosine multiplier that multiplies the cosine value of the first reversible counter by the signal at the first input terminal; a sine multiplier that inputs the output signal of the first reversible counter to and multiplies the signal at the first input terminal by the sine value of the first reversible counter; and outputs of the cosine multiplier and the sine multiplier. A subtracter that inputs a signal and outputs the difference between two signals, and a subtracter that inputs the output signal of the subtracter to the first input terminal of the two input terminals, inputs the carrier wave to the second input terminal, and inputs the carrier wave to the second input terminal. a phase detector that detects and rectifies the signal at the second input terminal using the signal at the second input terminal; The first reversible counter counts up or down by inputting the output signal of the phase detector to a first input terminal and inputting the clock signal of the voltage controlled oscillator to a second input terminal, and measures time. The output signal of the phase detector is input to the first input terminal of the three input terminals, the clock signal of the voltage controlled oscillator is input to the second input terminal, and the clock signal of the above-mentioned voltage controlled oscillator is input to the third input terminal. An analog counter characterized by comprising a second reversible counter that inputs a signal and counts up or down.
Digital conversion device. (2) A quadrant selector that inputs the sine wave and cosine wave signals of the resolver signal and outputs the quadrant-selected sine wave and cosine wave signals, and the quadrant selector at the first input end of the two input ends. a cosine multiplier that inputs a sine wave signal of , inputs the output signal of a first reversible counter to a second input terminal, and multiplies the signal of the first input terminal by the cosine value of the first reversible counter; The cosine wave signal of the quadrant selector is input to the first input terminal of the two input terminals, the output signal of the first reversible counter is input to the second input terminal, and the sine wave signal of the first reversible counter is input to the first input terminal of the two input terminals. a sine multiplier that multiplies the signal at the first input terminal by a value; a subtracter that inputs the output signals of the cosine multiplier and the sine multiplier and outputs the difference between the two signals; a phase detector that inputs the output signal of the subtracter to one input terminal, inputs a carrier wave to a second input terminal, and detects and rectifies the signal at the first input terminal with the signal at the second input terminal; A voltage controlled oscillator which inputs the output signal of a phase detector and whose oscillation frequency changes depending on the input signal; the first reversible counter which inputs the clock signal of the voltage controlled oscillator and counts up or down, and a timer which measures time;
The output signal of the phase detector is input to the first input terminal of the two input terminals, the clock signal of the voltage controlled oscillator is input to the second input terminal, and the signal of the timer is input to the third input terminal. or a second reversible counter that counters a falling count. (3) Input a 3-phase synchro signal and convert it into a 2-phase resolver signal. Input the sine wave signal of the output resolver signal of the above Scott transformer to the first input terminal of the two input terminals. 2nd
a cosine multiplier that inputs the output signal of a first reversible counter to an input terminal thereof and multiplies the signal of the first input terminal by the cosine value of the first reversible counter; and a first input terminal of the two input terminals. The cosine wave signal of the output resolver signal of the Scott transformer is input to the second input terminal, the output signal of the first reversible counter is input to the second input terminal, and the sine value of the first reversible counter is input to the first input terminal. a sine multiplier that multiplies the signal at the end; a subtracter that inputs the output signals of the cosine multiplier and the sine multiplier and outputs the difference between the two signals; a phase detector which inputs the output signal of the subtracter, inputs a carrier wave to a second input terminal, detects and rectifies the signal at the first input terminal with the signal at the second input terminal, and the output signal of the phase detector. A voltage controlled oscillator whose oscillation frequency changes depending on the input signal, and a voltage controlled oscillator whose oscillation frequency changes depending on the input signal, and a voltage controlled oscillator whose output signal from the phase detector is inputted to the first input terminal of the two input terminals and the clock signal of the voltage controlled oscillator is inputted to the second input terminal. the first reversible counter that inputs and counts up or down;
A timer that measures time and the first of three input terminals.
The output signal of the phase detector is inputted to the input terminal of , the clock signal of the voltage controlled oscillator is inputted to the second input terminal, and the signal of the above-mentioned timer is inputted to the third input terminal. An analog-to-digital conversion device comprising: 2 reversible counters. (4) A SCOTT transformer that inputs a 3-phase synchro signal and outputs a 2-phase resolver signal, and a sine wave whose quadrant is selected by inputting the sine wave and cosine wave signals of the resolver signal output from the SCOTT transformer. and a quadrant selector that outputs a cosine wave signal, and a sine wave signal of the quadrant selector is input to the first input terminal of the two input terminals, and an output signal of the first reversible counter is input to the second input terminal. a cosine multiplier that inputs the cosine value of the reversible counter and multiplies the signal at the first input terminal, and a cosine multiplier that inputs the cosine wave signal of the quadrant selector to the first input terminal of the two input terminals, and At the input end of
A sine multiplier that inputs the output signal of the reversible counter and multiplies the signal at the first input terminal by the sine value of the first reversible counter, and inputs the output signals of the cosine multiplier and the sine multiplier. A subtracter outputs the difference between two signals, and the output signal of the subtracter is input to the first input terminal of the two input terminals, the carrier wave is input to the second input terminal, and the signal at the first input terminal is input. a phase detector that detects and rectifies the signal at the second input terminal; a voltage-controlled oscillator that receives the output signal of the phase detector and whose oscillation frequency changes depending on the input signal; and a first input terminal of the two input terminals. the first reversible counter which inputs the output signal of the phase detector to the second input terminal and inputs the clock signal of the voltage controlled oscillator to the second input terminal to count rising or falling; and a timer which measures time; The output signal of the phase detector is input to the first input terminal of the two input terminals, the clock signal of the voltage controlled oscillator is input to the second input terminal, and the signal of the timer is input to the third input terminal. or a second reversible counter that counts the decline.
JP11988189U 1989-10-14 1989-10-14 Pending JPH0360018U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11988189U JPH0360018U (en) 1989-10-14 1989-10-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11988189U JPH0360018U (en) 1989-10-14 1989-10-14

Publications (1)

Publication Number Publication Date
JPH0360018U true JPH0360018U (en) 1991-06-13

Family

ID=31667977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11988189U Pending JPH0360018U (en) 1989-10-14 1989-10-14

Country Status (1)

Country Link
JP (1) JPH0360018U (en)

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