JPS63157614U - - Google Patents
Info
- Publication number
- JPS63157614U JPS63157614U JP5094387U JP5094387U JPS63157614U JP S63157614 U JPS63157614 U JP S63157614U JP 5094387 U JP5094387 U JP 5094387U JP 5094387 U JP5094387 U JP 5094387U JP S63157614 U JPS63157614 U JP S63157614U
- Authority
- JP
- Japan
- Prior art keywords
- resolver
- signal
- analog
- digital converter
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
は従来の変換器を示す図である。
図において、１は水晶発振器、２は分周器、３
はｓｉｎ／ｃｏｓ発振器、４はレゾルバの励磁信
号Ｖｓｉｎωｔ、５はレゾルバの励磁信号Ｖｃｏ
ｓωｔ、６はレゾルバ、７はタイミング発振器、
８はサンプル・ホールド回路、９はアナログ／デ
ジタル変換器、１０はメモリ、１１はデジタル出
力信号、１２は位相検出器、１３はカウンター、
１４はラツチ回路である。なお、各図中同一符号
は同一または相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional converter. In the figure, 1 is a crystal oscillator, 2 is a frequency divider, and 3
is a sin/cos oscillator, 4 is the resolver excitation signal Vsinωt, and 5 is the resolver excitation signal Vco.
sωt, 6 is a resolver, 7 is a timing oscillator,
8 is a sample and hold circuit, 9 is an analog/digital converter, 10 is a memory, 11 is a digital output signal, 12 is a phase detector, 13 is a counter,
14 is a latch circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
変換するサンプル・ホールド回路、サンプル・ホ
ールド回路からのアナログ信号をデジタル信号に
変換するアナログ／デジタル変換器と、前記二つ
の構成要素を制御するタイミング発振器と、前記
アナログ／デジタル変換器からのデジタル信号に
より、角度データのビツトパターンを出力するメ
モリとを備えたことを特徴とするレゾルバ／デジ
タル変換器。 a resolver, a sample and hold circuit that converts the signal from the resolver into DC, an analog/digital converter that converts the analog signal from the sample and hold circuit into a digital signal, and a timing oscillator that controls the two components. A resolver/digital converter comprising: a memory for outputting a bit pattern of angle data according to a digital signal from the analog/digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5094387U JPS63157614U (en) | 1987-04-03 | 1987-04-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5094387U JPS63157614U (en) | 1987-04-03 | 1987-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63157614U true JPS63157614U (en) | 1988-10-17 |
Family
ID=30874762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5094387U Pending JPS63157614U (en) | 1987-04-03 | 1987-04-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63157614U (en) |
-
1987
- 1987-04-03 JP JP5094387U patent/JPS63157614U/ja active Pending
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