JPS6430930U

JPS6430930U -

Info

Publication number: JPS6430930U
Application number: JP12578487U
Authority: JP
Priority date: 1987-08-18
Filing date: 1987-08-18
Publication date: 1989-02-27

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は従来の技術によるデジタルＰＬＬ回路の
一例を示すブロツク図、第３図ａおよびｂはそれ
ぞれ本考案の一実施例および従来の技術の例によ
る入出力信号のタイミング説明図である。１…固定周波数発振器、２…第一のサンプルタ
イミング発生回路、３…第二のサンプルタイミン
グ発生回路、４…カウンタ、５…出力レベル切換
回路、６…位相比較器、７…判定回路、８…ラツ
チ回路。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a digital PLL circuit according to the prior art, and FIGS. 3a and 3 b are timing diagrams of input and output signals according to an embodiment of the present invention and an example of the prior art, respectively. DESCRIPTION OF SYMBOLS 1... Fixed frequency oscillator, 2... First sample timing generation circuit, 3... Second sample timing generation circuit, 4... Counter, 5... Output level switching circuit, 6... Phase comparator, 7... Judgment circuit, 8... latch circuit.

Claims

[Scope of utility model registration request]

In a digital PLL circuit that reads the phase difference between input and output signals from the value of a counter to which the output of a fixed frequency oscillator is applied, and controls the phase of the output signal based on that value, a first sample timing generation circuit that outputs a timing signal for sampling an input signal at a predetermined timing to a phase comparator; A digital PLL circuit comprising: a second sample timing generation circuit that outputs a timing signal for sampling an input signal to the phase comparator.