JPS6430930U - - Google Patents

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Publication number
JPS6430930U
JPS6430930U JP12578487U JP12578487U JPS6430930U JP S6430930 U JPS6430930 U JP S6430930U JP 12578487 U JP12578487 U JP 12578487U JP 12578487 U JP12578487 U JP 12578487U JP S6430930 U JPS6430930 U JP S6430930U
Authority
JP
Japan
Prior art keywords
signal
timing
output
phase
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12578487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12578487U priority Critical patent/JPS6430930U/ja
Publication of JPS6430930U publication Critical patent/JPS6430930U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は従来の技術によるデジタルPLL回路の
一例を示すブロツク図、第3図aおよびbはそれ
ぞれ本考案の一実施例および従来の技術の例によ
る入出力信号のタイミング説明図である。 1…固定周波数発振器、2…第一のサンプルタ
イミング発生回路、3…第二のサンプルタイミン
グ発生回路、4…カウンタ、5…出力レベル切換
回路、6…位相比較器、7…判定回路、8…ラツ
チ回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a digital PLL circuit according to the prior art, and FIGS. 3a and 3 b are timing diagrams of input and output signals according to an embodiment of the present invention and an example of the prior art, respectively. DESCRIPTION OF SYMBOLS 1... Fixed frequency oscillator, 2... First sample timing generation circuit, 3... Second sample timing generation circuit, 4... Counter, 5... Output level switching circuit, 6... Phase comparator, 7... Judgment circuit, 8... latch circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 固定周波数発振器の出力が印加されるカウンタ
の値から入出力信号の位相差を読みとり、その値
により出力信号の位相を制御する方式のデジタル
PLL回路において、前記固定周波数発振器出力
の1周期のうちあらかじめ定められたタイミング
で入力信号をサンプリングするタイミング信号を
位相比較器へ出力する第一のサンプルタイミング
発生回路と、前記固定周波数発振器出力の1周期
のうち前記第一のタイミングと異なる第二のタイ
ミングで入力信号をサンプリングするタイミング
信号を前記位相比較器へ出力する第二のサンプル
タイミング発生回路とを備えてなることを特徴と
するデジタルPLL回路。
In a digital PLL circuit that reads the phase difference between input and output signals from the value of a counter to which the output of a fixed frequency oscillator is applied, and controls the phase of the output signal based on that value, a first sample timing generation circuit that outputs a timing signal for sampling an input signal at a predetermined timing to a phase comparator; A digital PLL circuit comprising: a second sample timing generation circuit that outputs a timing signal for sampling an input signal to the phase comparator.
JP12578487U 1987-08-18 1987-08-18 Pending JPS6430930U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12578487U JPS6430930U (en) 1987-08-18 1987-08-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12578487U JPS6430930U (en) 1987-08-18 1987-08-18

Publications (1)

Publication Number Publication Date
JPS6430930U true JPS6430930U (en) 1989-02-27

Family

ID=31376699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12578487U Pending JPS6430930U (en) 1987-08-18 1987-08-18

Country Status (1)

Country Link
JP (1) JPS6430930U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225927A (en) * 1985-03-30 1986-10-07 Toshiba Corp Phase comparator of digital logic pll circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225927A (en) * 1985-03-30 1986-10-07 Toshiba Corp Phase comparator of digital logic pll circuit

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