JPS6047357U - Clock generation circuit - Google Patents
Clock generation circuitInfo
- Publication number
- JPS6047357U JPS6047357U JP13994483U JP13994483U JPS6047357U JP S6047357 U JPS6047357 U JP S6047357U JP 13994483 U JP13994483 U JP 13994483U JP 13994483 U JP13994483 U JP 13994483U JP S6047357 U JPS6047357 U JP S6047357U
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase difference
- circuit
- frequency
- reference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例を示すブロック図、第２図は本考案の一
実施例を示すブロック図である。
１・・・・・・発振回路、２・・・・・・分周回路、３
・・・・・・選択回路、４・・・・・・位相比較回路、
５・・・・・・分周回路、６・・・・・・位相差検出回
路。FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Oscillation circuit, 2... Frequency dividing circuit, 3
...Selection circuit, 4...Phase comparison circuit,
5... Frequency divider circuit, 6... Phase difference detection circuit.
Claims (1)
、゛この分周手段の出力と基準信号の位相を比較する手
段と、この比較手段の出力に応じて前記分周手段の分周
比を設定する選択回路とを有するクロック作成回路にお
いて、前記比較手段が前記基準信号と前記出力信号の位
相差を検出する回路を有し、前記分周手段が前記検出回
路の出力に応じて分周比を、前記位相差が所定値より大
の場合は、ｉ下■又はｎｔｋに、前記位相差がその所定
値より小の場合は正１又は 。＋１ （ｎｔ ｋは２以
上の整数）に設定することを特徴とするクロック作成回
路。an oscillation circuit; a frequency dividing means for frequency dividing the output of the oscillation circuit; a means for comparing the phase of the output of the frequency dividing means with the phase of a reference signal; and a selection circuit for setting a frequency ratio, wherein the comparison means includes a circuit for detecting a phase difference between the reference signal and the output signal, and the frequency division means detects a phase difference between the reference signal and the output signal according to the output of the detection circuit. When the phase difference is larger than a predetermined value, the frequency division ratio is set to i lower ■ or ntk, and when the phase difference is smaller than the predetermined value, it is set to positive 1 or ntk. +1 (nt k is an integer of 2 or more).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13994483U JPS6047357U (en) | 1983-09-09 | 1983-09-09 | Clock generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13994483U JPS6047357U (en) | 1983-09-09 | 1983-09-09 | Clock generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6047357U true JPS6047357U (en) | 1985-04-03 |
Family
ID=30313497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13994483U Pending JPS6047357U (en) | 1983-09-09 | 1983-09-09 | Clock generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047357U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175427A (en) * | 1987-12-29 | 1989-07-11 | Matsushita Electric Ind Co Ltd | Bit synchronizing circuit |
-
1983
- 1983-09-09 JP JP13994483U patent/JPS6047357U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175427A (en) * | 1987-12-29 | 1989-07-11 | Matsushita Electric Ind Co Ltd | Bit synchronizing circuit |
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