JPS6416198U

JPS6416198U -

Info

Publication number: JPS6416198U
Application number: JP1987110980U
Authority: JP
Priority date: 1987-07-20
Filing date: 1987-07-20
Publication date: 1989-01-26

Description

[Brief explanation of drawings]

第１図〜第４図は本考案に係り第１図は第１の
実施例のブロツク図、第２図はその波形図、第３
図は第２実施例のブロツク図、第４図はその波形
図ある。第５図は従来例のブロツク図、第６図は
その波形図である。３……速度ロツク検出回路、８，２１……遅延
手段（モノマルチ）、１１……Ｄ型フリツプフロ
ツプ、５，２０……分周器。 Figures 1 to 4 relate to the present invention; Figure 1 is a block diagram of the first embodiment, Figure 2 is a waveform diagram thereof, and Figure 3 is a block diagram of the first embodiment.
The figure is a block diagram of the second embodiment, and FIG. 4 is its waveform diagram. FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a waveform diagram thereof. 3... Speed lock detection circuit, 8, 21... Delay means (monomulti), 11... D-type flip-flop, 5, 20... Frequency divider.

Claims

[Scope of utility model registration request]

In a servo circuit having speed control and phase control that performs a phase comparison between a phase detection signal of a controlled object and a reference signal, a detection circuit that detects that the speed of the controlled object is within a predetermined range, and a detection circuit that detects that the speed of the controlled object is within a predetermined range; a delay means for delaying the phase detection signal; a means for detecting the phase of the output of the delay means immediately after the speed falls within a predetermined range; and a means for detecting the phase of the output of the delay means immediately after the speed falls within a predetermined range; A servo circuit characterized by comprising a frequency divider.