JPH0236230U - - Google Patents
Info
- Publication number
- JPH0236230U JPH0236230U JP11610888U JP11610888U JPH0236230U JP H0236230 U JPH0236230 U JP H0236230U JP 11610888 U JP11610888 U JP 11610888U JP 11610888 U JP11610888 U JP 11610888U JP H0236230 U JPH0236230 U JP H0236230U
- Authority
- JP
- Japan
- Prior art keywords
- plo
- phase
- oscillator
- output
- adjustment circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例によるＰＬＯフリ
ーラン調整回路のブロツク図、第２図、第３図は
この考案の他の実施例を示すＰＬＯフリーラン調
整回路のブロツク図、第４図は従来のＰＬＯフリ
ーラン調整回路のブロツク図である。図において
、５は制御回路、６は監視回路を示す。なお、図
中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram of a PLO free run adjustment circuit according to one embodiment of this invention, FIGS. 2 and 3 are block diagrams of a PLO free run adjustment circuit showing other embodiments of this invention, and FIG. 4 is a block diagram of a PLO free run adjustment circuit according to an embodiment of this invention. 1 is a block diagram of a conventional PLO free run adjustment circuit; FIG. In the figure, 5 indicates a control circuit, and 6 indicates a monitoring circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
をフイードバツクすることによつて可変発振器の
位相を基準発振器の位相に一致させるＰＬＯフリ
ーラン調整回路において、監視回路と制御回路を
設けたことにより、基本信号の入力断状態にも対
応が可能としたことを特徴とするＰＬＯフリーラ
ン調整回路。 In the PLO free-run adjustment circuit that matches the phase of the variable oscillator with the phase of the reference oscillator by feeding back the phase difference between the output of the reference oscillator and the output of the variable oscillator, the provision of a monitoring circuit and a control circuit makes it possible to A PLO free run adjustment circuit characterized by being able to cope with a signal input cutoff state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11610888U JPH0236230U (en) | 1988-09-01 | 1988-09-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11610888U JPH0236230U (en) | 1988-09-01 | 1988-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236230U true JPH0236230U (en) | 1990-03-08 |
Family
ID=31358346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11610888U Pending JPH0236230U (en) | 1988-09-01 | 1988-09-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236230U (en) |
-
1988
- 1988-09-01 JP JP11610888U patent/JPH0236230U/ja active Pending