JPH0239176U - - Google Patents

Info

Publication number
JPH0239176U
JPH0239176U JP11877388U JP11877388U JPH0239176U JP H0239176 U JPH0239176 U JP H0239176U JP 11877388 U JP11877388 U JP 11877388U JP 11877388 U JP11877388 U JP 11877388U JP H0239176 U JPH0239176 U JP H0239176U
Authority
JP
Japan
Prior art keywords
under test
signal under
signal
synchronization
gate circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11877388U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11877388U priority Critical patent/JPH0239176U/ja
Publication of JPH0239176U publication Critical patent/JPH0239176U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Measuring Frequencies, Analyzing Spectra (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のブロツク構成図、
第2図は該一実施例のおける動作の流れ図、第3
図は該一実施例の動作タイミング図、第4図は従
来装置のブロツク構成図、第5図は従来装置の動
作の流れ図、第6図は従来装置で計数誤差が起こ
らない場合の動作タイミング図、第7図は従来装
置で計数誤差が起こる場合の動作タイミング図で
ある。
FIG. 1 is a block diagram of an embodiment of the present invention.
Figure 2 is a flowchart of the operation in this embodiment;
4 is a block diagram of the conventional device, FIG. 5 is a flowchart of the operation of the conventional device, and FIG. 6 is an operational timing diagram of the conventional device when no counting error occurs. , FIG. 7 is an operation timing diagram when a counting error occurs in the conventional device.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被測定信号をゲート回路により一定時間とり込
んで計数を行なう周波数計数装置において、被測
定信号の一部を取り出して基準信号発振器及びタ
イミング制御部に印加し、ゲート回路の制御信号
を被測定信号に同期させる同期回路を有すること
を特徴とする周波数計数装置。
In a frequency counting device that performs counting by taking in a signal under test for a certain period of time using a gate circuit, a part of the signal under test is taken out and applied to a reference signal oscillator and a timing control section, and the control signal of the gate circuit is converted into the signal under test. A frequency counting device characterized by having a synchronization circuit for synchronization.
JP11877388U 1988-09-09 1988-09-09 Pending JPH0239176U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11877388U JPH0239176U (en) 1988-09-09 1988-09-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11877388U JPH0239176U (en) 1988-09-09 1988-09-09

Publications (1)

Publication Number Publication Date
JPH0239176U true JPH0239176U (en) 1990-03-15

Family

ID=31363413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11877388U Pending JPH0239176U (en) 1988-09-09 1988-09-09

Country Status (1)

Country Link
JP (1) JPH0239176U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008114602A1 (en) * 2007-03-20 2008-09-25 Advantest Corporation Test equipment and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008114602A1 (en) * 2007-03-20 2008-09-25 Advantest Corporation Test equipment and electronic device

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