JPH0390568U - - Google Patents
Info
- Publication number
- JPH0390568U JPH0390568U JP15291189U JP15291189U JPH0390568U JP H0390568 U JPH0390568 U JP H0390568U JP 15291189 U JP15291189 U JP 15291189U JP 15291189 U JP15291189 U JP 15291189U JP H0390568 U JPH0390568 U JP H0390568U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- output
- reference clock
- vertical synchronization
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000007493 shaping process Methods 0.000 claims 2
- 239000002131 composite material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は同実施例の動作を説明するためのタイミ
ングチヤート、第３図は従来の垂直同期信号検出
回路を示すブロツク図、第４図は同実施例の動作
を説明するためのタイミングチヤートである。
３１……フリツプフロツプ、３３……アツプカ
ウンタ、３４……デコーダ、３５，３６……フリ
ツプフロツプ。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a timing chart for explaining the operation of the same embodiment, Fig. 3 is a block diagram showing a conventional vertical synchronization signal detection circuit, and Fig. 4 is a timing chart for explaining the operation of the same embodiment. be. 31...Flip-flop, 33...Up counter, 34...Decoder, 35, 36...Flip-flop.
Claims (1)
この手段により波形整形された信号が有意レベル
となつている間のみ基準クロツクを出力する基準
クロツク出力手段と、この手段から出力される基
準クロツクによりカウントアツプ動作し、一定期
間毎にリセツトされるアツプカウンタと、このア
ツプカウンタのカウント値が設定値ｎに達した状
態を検出するデコーダと、このデコーダの出力信
号に基づいて所定時間幅の垂直同期信号を発生す
る垂直同期信号発生手段とを具備したことを特徴
とする垂直同期信号検出回路。 a waveform shaping means for shaping the composite synchronization signal;
A reference clock output means outputs a reference clock only while the signal waveform-shaped by this means is at a significant level, and an output clock that performs a count-up operation using the reference clock output from this means and is reset at regular intervals. The device includes a counter, a decoder that detects when the count value of the up counter reaches a set value n, and vertical synchronization signal generating means that generates a vertical synchronization signal of a predetermined time width based on the output signal of the decoder. A vertical synchronization signal detection circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15291189U JPH0390568U (en) | 1989-12-28 | 1989-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15291189U JPH0390568U (en) | 1989-12-28 | 1989-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0390568U true JPH0390568U (en) | 1991-09-13 |
Family
ID=31699147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15291189U Pending JPH0390568U (en) | 1989-12-28 | 1989-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0390568U (en) |
-
1989
- 1989-12-28 JP JP15291189U patent/JPH0390568U/ja active Pending
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