JPS6413868U - - Google Patents
Info
- Publication number
- JPS6413868U JPS6413868U JP10782187U JP10782187U JPS6413868U JP S6413868 U JPS6413868 U JP S6413868U JP 10782187 U JP10782187 U JP 10782187U JP 10782187 U JP10782187 U JP 10782187U JP S6413868 U JPS6413868 U JP S6413868U
- Authority
- JP
- Japan
- Prior art keywords
- generation circuit
- pseudo
- reference signal
- signal
- signal generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronizing For Television (AREA)
- Television Signal Processing For Recording (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は波形図である。
９……基準信号発生回路、１６……擬似垂直同
期信号発生回路、１７，１８……ＡＮＤゲート。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a waveform diagram. 9... Reference signal generation circuit, 16... Pseudo vertical synchronization signal generation circuit, 17, 18... AND gate.
Claims (1)
準信号発生回路と、この基準信号発生回路の出力
に基づいて擬似垂直同期信号を作成する作成回路
と、メモリ手段を利用しない特殊再生モードにお
いて前記カウンタをＲＦスイツチングパルスに基
づいてセツト、リセツトする手段よりなる擬似垂
直同基信号作成装置。 a reference signal generation circuit having a counter that frequency-divides a predetermined oscillation signal; a generation circuit that generates a pseudo vertical synchronization signal based on the output of the reference signal generation circuit; A device for creating a pseudo-vertical same-base signal, comprising means for setting and resetting based on RF switching pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10782187U JPS6413868U (en) | 1987-07-14 | 1987-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10782187U JPS6413868U (en) | 1987-07-14 | 1987-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6413868U true JPS6413868U (en) | 1989-01-24 |
Family
ID=31342579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10782187U Pending JPS6413868U (en) | 1987-07-14 | 1987-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6413868U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5696581A (en) * | 1979-12-29 | 1981-08-04 | Sony Corp | Generating circuit for vertical blanking signal and virtual vertical synchronizing signal |
-
1987
- 1987-07-14 JP JP10782187U patent/JPS6413868U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5696581A (en) * | 1979-12-29 | 1981-08-04 | Sony Corp | Generating circuit for vertical blanking signal and virtual vertical synchronizing signal |