JPS6368259U - - Google Patents
Info
- Publication number
- JPS6368259U JPS6368259U JP16005286U JP16005286U JPS6368259U JP S6368259 U JPS6368259 U JP S6368259U JP 16005286 U JP16005286 U JP 16005286U JP 16005286 U JP16005286 U JP 16005286U JP S6368259 U JPS6368259 U JP S6368259U
- Authority
- JP
- Japan
- Prior art keywords
- down counter
- count
- clock pulse
- value
- selecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案による同期信号検出回路の構成
を示す図、第２図及び第３図は同実施例の動作を
説明するためのタイミングチヤート、第４図は従
来の同期信号検出回路の構成を示す図、第５図は
第４図の動作を説明するためのタイミングチヤー
トである。
１１……アツプ／ダウンカウンタ、１２，１５
，１７，２２，２３……アンド回路、１４，１８
〜２１……インバータ、１３，１６……ノア回路
。
FIG. 1 is a diagram showing the configuration of a synchronization signal detection circuit according to the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of the same embodiment, and FIG. 4 is the configuration of a conventional synchronization signal detection circuit. FIG. 5 is a timing chart for explaining the operation of FIG. 4. 11... Up/down counter, 12, 15
, 17, 22, 23...AND circuit, 14, 18
~21...Inverter, 13,16...NOR circuit.
Claims (1)
れている時に第１のクロツクパルスを選択して上
記アツプ／ダウンカウンタをカウントアツプする
手段と、上記同期信号が与えられていない間第２
のクロツクパルスを選択して上記アツプ／ダウン
カウンタをカウントダウンする手段と、上記アツ
プ／ダウンカウンタのカウント値が設定値以上に
なつた時にその状態を検出して同期検出信号を出
力する手段と、上記アツプ／ダウンカウンタのカ
ウント値が上限設定値または下限設定値に達した
際にカウント動作を停止する手段とを具備したこ
とを特徴とする同期信号検出回路。 an up/down counter; means for selecting a first clock pulse to count up the up/down counter when the synchronization signal is not applied; and a second clock pulse when the synchronization signal is not applied;
means for selecting the clock pulse of the up/down counter to count down the up/down counter; means for detecting the state when the count value of the up/down counter exceeds a set value and outputting a synchronization detection signal; 1. A synchronizing signal detection circuit comprising: means for stopping a counting operation when the count value of a down counter reaches an upper limit setting value or a lower limit setting value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16005286U JPS6368259U (en) | 1986-10-21 | 1986-10-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16005286U JPS6368259U (en) | 1986-10-21 | 1986-10-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6368259U true JPS6368259U (en) | 1988-05-09 |
Family
ID=31085062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16005286U Pending JPS6368259U (en) | 1986-10-21 | 1986-10-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6368259U (en) |
-
1986
- 1986-10-21 JP JP16005286U patent/JPS6368259U/ja active Pending