JPS63171027U

JPS63171027U -

Info

Publication number: JPS63171027U
Application number: JP6279487U
Authority: JP
Priority date: 1987-04-24
Filing date: 1987-04-24
Publication date: 1988-11-08

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、第２
図は従来例の一実施例を示す回路図、第３図は第
２図図示従来例を示す回路図の動作を説明する為
のタイミングチヤート、第４図は、第１図図示回
路図の動作を説明する為のタイミングチヤートで
ある。図中１，２，３はフリツプフロツプ回路、４，
６，８，９はＡＮＤ回路、５，７はＮＯＴ回路、
１０はＯＲ回路を表す。 Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing an example of the conventional example, Figure 3 is a timing chart for explaining the operation of the circuit diagram shown in Figure 2 which shows the conventional example, and Figure 4 is the operation of the circuit diagram shown in Figure 1. This is a timing chart to explain. In the figure, 1, 2, 3 are flip-flop circuits, 4,
6, 8, 9 are AND circuits, 5, 7 are NOT circuits,
10 represents an OR circuit.

Claims

[Scope of utility model registration request]

A first flip-flop circuit performs a latch operation based on changes in the basic clock signal, and a reset operation is controlled by a trigger signal and an output from the second flip-flop circuit, and a clock signal whose polarity is inverted from the basic clock signal. a second flip-flop circuit that performs a latch operation based on the change in the flip-flop circuit and whose reset operation is controlled by the trigger signal and the output from the first flip-flop circuit; and a third flip-flop circuit whose latch operation is controlled by the basic clock signal. 2. A timing circuit comprising: a third flip-flop circuit, wherein the output from the third flip-flop circuit changes in synchronization with a second change in the clock signal after the trigger signal changes.