JPS63155529U - - Google Patents
Info
- Publication number
- JPS63155529U JPS63155529U JP4710187U JP4710187U JPS63155529U JP S63155529 U JPS63155529 U JP S63155529U JP 4710187 U JP4710187 U JP 4710187U JP 4710187 U JP4710187 U JP 4710187U JP S63155529 U JPS63155529 U JP S63155529U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- master clock
- generation circuit
- slave
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の実施例を示すブロツク図、第
２図は本考案実施例の動作を示すタイミングチヤ
ート、第３図、第４図は従来の同期制御回路の構
成例を示すブロツク図である。
１１…マスタクロツク発生回路、１２…主同期
制御回路、１３，１４…スレーブクロツク発生回
路、１５，１６…副同期制御回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of the present invention, and FIGS. 3 and 4 are block diagrams showing an example of the configuration of a conventional synchronous control circuit. be. 11...Master clock generation circuit, 12...Main synchronous control circuit, 13, 14...Slave clock generation circuit, 15, 16...Sub synchronous control circuit.
Claims (1)
波数の同期クロツクを生成するマスタクロツク生
成回路と、上記同期クロツクを得、同位相の任意
周波数のスレーブクロツクを生成するスレーブク
ロツク発生回路と、上記マスタクロツク発生回路
に接続され、マスタクロツクにより動作する主同
期制御回路と、上記スレーブクロツク発生回路に
接続され、スレーブクロツクにより動作する少く
とも１組の副同期制御回路とを具備することを特
徴とする同期制御回路。 a master clock generation circuit that generates a master clock and a synchronous clock of an arbitrary frequency having the same phase as the master clock; a slave clock generation circuit that obtains the synchronous clock and generates a slave clock of an arbitrary frequency of the same phase; and the master clock generation circuit A synchronous control circuit comprising a main synchronous control circuit connected to the master clock and operated by a master clock, and at least one set of sub synchronous control circuits connected to the slave clock generation circuit and operated by the slave clock. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4710187U JPS63155529U (en) | 1987-03-30 | 1987-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4710187U JPS63155529U (en) | 1987-03-30 | 1987-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155529U true JPS63155529U (en) | 1988-10-12 |
Family
ID=30867381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4710187U Pending JPS63155529U (en) | 1987-03-30 | 1987-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155529U (en) |
-
1987
- 1987-03-30 JP JP4710187U patent/JPS63155529U/ja active Pending
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