JPS6210546U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 shows a clock generation circuit according to an embodiment of the present invention, FIG. 2 is a principle diagram of a conventional communication control clock generation circuit, FIGS. 3 and 5 are time charts of signals generated by the conventional clock generation circuit, and FIG. The figure is a basic circuit diagram of a conventional clock generation circuit, and FIG. 6 is a time chart of FIG. 1. 21: Counter preset input terminal, 22: Counter start/stop control signal, 23: Counter clock input signal, 24: Communication clock output terminal.

Claims (1)

[Scope of utility model registration request] External devices connected to the CPU data bus
A signal processing device in which a CPU performs synchronous communication processing between the CPU and the external device obtains data access timing with an external device from the output of a synchronization clock signal generation circuit, generates a synchronization clock signal necessary for executing input/output of the CPU. A counter, an input terminal for setting the initial state of this counter, and when the CPU executes data input/output operation to an external device, the counter initial setting input is taken into the counter, and the output of the counter is used to access the CPU. A clock generation circuit characterized in that it is provided with means.