JPS6251428U - - Google Patents
Info
- Publication number
- JPS6251428U JPS6251428U JP14170285U JP14170285U JPS6251428U JP S6251428 U JPS6251428 U JP S6251428U JP 14170285 U JP14170285 U JP 14170285U JP 14170285 U JP14170285 U JP 14170285U JP S6251428 U JPS6251428 U JP S6251428U
- Authority
- JP
- Japan
- Prior art keywords
- reset signal
- control circuit
- peripheral device
- external peripheral
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 3
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Retry When Errors Occur (AREA)
Description
第１図は本考案回路の１実施例の回路構成図、
第２図は従来回路の構成図である。
１…ＭＰＵ、４，６…メモリ、７…制御回路部
、９…リセツト信号発生部、１０…ゲート回路。
FIG. 1 is a circuit configuration diagram of one embodiment of the circuit of the present invention,
FIG. 2 is a block diagram of a conventional circuit. DESCRIPTION OF SYMBOLS 1... MPU, 4, 6... Memory, 7... Control circuit part, 9... Reset signal generation part, 10... Gate circuit.
Claims (1)
を有するＭＰＵと、該ＭＰＵによつて制御されデ
ータバス上に所定のデータを出力するメモリと、
前記データバス上のデータと前記リセツト信号と
を入力して、外部周辺機器に対して所定の制御信
号を付与する出力端子を有する制御回路部と、前
記リセツト信号入力端子にリセツト信号を付与す
るためのリセツト信号発生部とを備える外部周辺
機器の制御回路において、前記制御回路部は前記
データバスからプログラム異常を示すデータを受
けたとき前記リセツト信号発生部からのリセツト
信号に相当するリセツト信号を出力する出力端子
を備え、このリセツト出力端子と前記リセツト信
号発生部との各リセツト信号を２入力とし、出力
が前記リセツト信号入力端子に付与されるゲート
回路とを備えてなる外部周辺機器の制御回路。 an MPU having a reset signal input terminal that receives a reset signal; a memory that is controlled by the MPU and outputs predetermined data onto a data bus;
a control circuit unit having an output terminal for inputting data on the data bus and the reset signal and applying a predetermined control signal to an external peripheral device; and a control circuit unit for applying a reset signal to the reset signal input terminal. A control circuit for an external peripheral device comprising a reset signal generating section, wherein the control circuit section outputs a reset signal corresponding to the reset signal from the reset signal generating section when receiving data indicating a program abnormality from the data bus. A control circuit for an external peripheral device, comprising: an output terminal, a gate circuit having two inputs for each reset signal of the reset output terminal and the reset signal generating section, and an output provided to the reset signal input terminal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14170285U JPS6251428U (en) | 1985-09-17 | 1985-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14170285U JPS6251428U (en) | 1985-09-17 | 1985-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6251428U true JPS6251428U (en) | 1987-03-31 |
Family
ID=31049735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14170285U Pending JPS6251428U (en) | 1985-09-17 | 1985-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6251428U (en) |
-
1985
- 1985-09-17 JP JP14170285U patent/JPS6251428U/ja active Pending
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