JPS63118601U - - Google Patents

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Publication number
JPS63118601U
JPS63118601U JP777087U JP777087U JPS63118601U JP S63118601 U JPS63118601 U JP S63118601U JP 777087 U JP777087 U JP 777087U JP 777087 U JP777087 U JP 777087U JP S63118601 U JPS63118601 U JP S63118601U
Authority
JP
Japan
Prior art keywords
output
terminal
supplied
input
gate circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP777087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP777087U priority Critical patent/JPS63118601U/ja
Publication of JPS63118601U publication Critical patent/JPS63118601U/ja
Pending legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案実施例のブロツク図、第2図A
,B,Cは本考案実施例のタイムチヤートを示し
、図AはRSF/Fの出力のタイムチヤート、図
Bはプログラムブル入出力ポートの出力のタイム
チヤート、図Cは最終出力のタイムチヤート、第
3図、第4図及び第5図は従来装置のブロツク図
である。 1……プログラマブル入出力IC、4,5……
プルアツプ抵抗、8,9……出力ポート、10…
…バス、11……リセツト信号、16……RSF
/F。
Figure 1 is a block diagram of an embodiment of the invention, Figure 2A
, B and C show time charts of the embodiment of the present invention, Figure A is a time chart of the output of RSF/F, Figure B is a time chart of the output of the programmable input/output port, Figure C is a time chart of the final output, FIGS. 3, 4 and 5 are block diagrams of conventional devices. 1...Programmable input/output IC, 4, 5...
Pull-up resistor, 8, 9... Output port, 10...
...Bus, 11...Reset signal, 16...RSF
/F.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プログラマブル入出力ICと、このICの出力
が第1入力端に供給されるゲート回路と、前記I
Cの出力がセツト端子に加えられるとともにリセ
ツト端子に前記ICに供給されるリセツト信号が
加えられかつ出力が前記ゲート回路の第2入力端
に供給されるプリツプ・フロツプ回路とを備える
ことを特徴とするプログラマブル入出力ICの制
御装置。
a programmable input/output IC; a gate circuit to which the output of the IC is supplied to a first input terminal;
and a pre-flop circuit to which an output of C is applied to a set terminal, a reset signal supplied to the IC is applied to a reset terminal, and an output is supplied to a second input terminal of the gate circuit. Control device for programmable input/output IC.
JP777087U 1987-01-22 1987-01-22 Pending JPS63118601U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP777087U JPS63118601U (en) 1987-01-22 1987-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP777087U JPS63118601U (en) 1987-01-22 1987-01-22

Publications (1)

Publication Number Publication Date
JPS63118601U true JPS63118601U (en) 1988-08-01

Family

ID=30791534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP777087U Pending JPS63118601U (en) 1987-01-22 1987-01-22

Country Status (1)

Country Link
JP (1) JPS63118601U (en)

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