JPH026339U - - Google Patents

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Publication number
JPH026339U
JPH026339U JP8362888U JP8362888U JPH026339U JP H026339 U JPH026339 U JP H026339U JP 8362888 U JP8362888 U JP 8362888U JP 8362888 U JP8362888 U JP 8362888U JP H026339 U JPH026339 U JP H026339U
Authority
JP
Japan
Prior art keywords
register
output signal
addition data
counter
full adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8362888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8362888U priority Critical patent/JPH026339U/ja
Publication of JPH026339U publication Critical patent/JPH026339U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路図、第2図は
従来の加算回路の回路図である。 1……第1のレジスタ、1C……クロツク端子
、1D……入力端子、1Q……出力端子、2……
第2のレジスタ、2Q……出力端子、3……全加
算器、3A,3B……入力端子、3S……出力端
子、4……カウンタ、4C……クロツク端子、4
Q……出力端子、4R……リセツト端子、5……
セレクタ、5A,5B……入力端子、5C……設
定端子、5Q……出力端子。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional adder circuit. 1...First register, 1C...Clock terminal, 1D...Input terminal, 1Q...Output terminal, 2...
2nd register, 2Q...Output terminal, 3...Full adder, 3A, 3B...Input terminal, 3S...Output terminal, 4...Counter, 4C...Clock terminal, 4
Q...Output terminal, 4R...Reset terminal, 5...
Selector, 5A, 5B...input terminal, 5C...setting terminal, 5Q...output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1、第2の2個のレジスタと全加算器とを有
する加算回路において、試験用に用いられるカウ
ンタと、前記第2のレジスタの出力信号と前記カ
ウンタの出力信号とのいずれか一方を選択して前
記全加算器の加算データ端子の一方に供給するセ
レクタとを備えることを特徴とする加算回路。
In an adder circuit having two registers, a first and second register, and a full adder, a counter used for testing, and either an output signal of the second register or an output signal of the counter are selected. and a selector for supplying the addition data to one of the addition data terminals of the full adder.
JP8362888U 1988-06-23 1988-06-23 Pending JPH026339U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8362888U JPH026339U (en) 1988-06-23 1988-06-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8362888U JPH026339U (en) 1988-06-23 1988-06-23

Publications (1)

Publication Number Publication Date
JPH026339U true JPH026339U (en) 1990-01-17

Family

ID=31308342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8362888U Pending JPH026339U (en) 1988-06-23 1988-06-23

Country Status (1)

Country Link
JP (1) JPH026339U (en)

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