JPH02138304U

JPH02138304U -

Info

Publication number: JPH02138304U
Application number: JP4482789U
Authority: JP
Priority date: 1989-04-17
Filing date: 1989-04-17
Publication date: 1990-11-19

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロツク図、
第２図はＩ／Ｏアドレスの割付け例を示す図、第
３図は従来のプログラマブル・コントローラを示
すブロツク図、第４図はＩ／Ｏアドレスの割付け
例を示す図、第５図はプロセツサ１０と増設Ｉ／
Ｏインターフエースの間に６４点分のダミー入出
力装置２８を取り付けた例を示すブロツク図、第
６図はＩ／Ｏアドレスの割付け例を示す図である
。１……基本Ｉ／Ｏ、２……増設Ｉ／Ｏ、３……
ケーブル、１０……プロセツサ、１１……増設Ｉ
／Ｏインターフエース、２０〜２７……入出力装
置、２８……ダミー入出力装置、３０……Ｉ／Ｏ
領域、４０……入出力装置２０のデータ転送領域
、４１……入出力装置２１のデータ転送領域、４
２……入出力装置２２のデータ転送領域、４３…
…入出力装置２３のデータ転送領域、４４……入
出力装置２４のデータ転送領域、４８……ダミー
入出力装置２８のデータ転送領域、５０……Ｉ／
Ｏアドレス設定スイツチ。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing an example of I/O address allocation, FIG. 3 is a block diagram showing a conventional programmable controller, FIG. 4 is a diagram showing an example of I/O address allocation, and FIG. 5 is a diagram showing an example of I/O address allocation. and expansion I/
A block diagram showing an example in which 64 dummy input/output devices 28 are installed between the O interfaces, and FIG. 6 is a diagram showing an example of I/O address assignment. 1... Basic I/O, 2... Expansion I/O, 3...
Cable, 10... Processor, 11... Extension I
/O interface, 20-27...I/O device, 28...Dummy input/output device, 30...I/O
Area, 40... Data transfer area of input/output device 20, 41... Data transfer area of input/output device 21, 4
2...Data transfer area of input/output device 22, 43...
...Data transfer area of input/output device 23, 44...Data transfer area of input/output device 24, 48...Data transfer area of dummy input/output device 28, 50...I/
O address setting switch.

Claims

[Scope of utility model registration request]

A programmable controller characterized by having an I/O address setting switch on an expansion I/O interface.