JPS6168400U - - Google Patents

Info

Publication number
JPS6168400U
JPS6168400U JP15161284U JP15161284U JPS6168400U JP S6168400 U JPS6168400 U JP S6168400U JP 15161284 U JP15161284 U JP 15161284U JP 15161284 U JP15161284 U JP 15161284U JP S6168400 U JPS6168400 U JP S6168400U
Authority
JP
Japan
Prior art keywords
input
output
signal
refresh
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15161284U
Other languages
Japanese (ja)
Other versions
JPH056639Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984151612U priority Critical patent/JPH056639Y2/ja
Publication of JPS6168400U publication Critical patent/JPS6168400U/ja
Application granted granted Critical
Publication of JPH056639Y2 publication Critical patent/JPH056639Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の実施例を示し、第１図は制御装
置の構成図、第２図は同装置のリフレツシユ動作
を説明するためのタイミングチヤートである。 １…制御装置、２…ダイナミツクＲＡＭ、４…
ＤＭＡ、６…リフレツシユ回路。 The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a control device, and FIG. 2 is a timing chart for explaining the refresh operation of the device. 1...Control device, 2...Dynamic RAM, 4...
DMA, 6...Refresh circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ダイナミツクＲＡＭと、入出力デバイスに対し
て入出力要求信号を出力する入出力要求端子を有
するＤＭＡとを備えた制御装置において、前記ダ
イナミツクＲＡＭとＤＭＡとの間に前記ＤＭＡの
入出力要求端子から出力される入出力要求信号と
システムクロツクとが共に入力されたときにこれ
に応答してリフレツシユ信号を出力するリフレツ
シユ回路を設け、このリフレツシユ回路から出力
されるリフレツシユ信号に基づいて入出力サイク
ル中に前記ダイナミツクＲＡＭをリフレツシユす
ることを特徴とする制御装置。 In a control device comprising a dynamic RAM and a DMA having an input/output request terminal for outputting an input/output request signal to an input/output device, an output signal is output from the input/output request terminal of the DMA between the dynamic RAM and the DMA. A refresh circuit is provided which outputs a refresh signal in response to input of both the input/output request signal and the system clock, and the refresh circuit outputs a refresh signal during the input/output cycle based on the refresh signal output from the refresh circuit. A control device characterized in that the dynamic RAM is refreshed.
JP1984151612U 1984-10-05 1984-10-05 Expired - Lifetime JPH056639Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984151612U JPH056639Y2 (en) 1984-10-05 1984-10-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984151612U JPH056639Y2 (en) 1984-10-05 1984-10-05

Publications (2)

Publication Number Publication Date
JPS6168400U true JPS6168400U (en) 1986-05-10
JPH056639Y2 JPH056639Y2 (en) 1993-02-19

Family

ID=30709720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984151612U Expired - Lifetime JPH056639Y2 (en) 1984-10-05 1984-10-05

Country Status (1)

Country Link
JP (1) JPH056639Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159292A (en) * 1982-03-17 1983-09-21 Hitachi Ltd Memory refreshing method
JPS5965998A (en) * 1982-10-07 1984-04-14 Mitsubishi Electric Corp Refreshing system of dynamic memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159292A (en) * 1982-03-17 1983-09-21 Hitachi Ltd Memory refreshing method
JPS5965998A (en) * 1982-10-07 1984-04-14 Mitsubishi Electric Corp Refreshing system of dynamic memory

Also Published As

Publication number Publication date
JPH056639Y2 (en) 1993-02-19

Similar Documents

Publication Publication Date Title
JPS6168400U (en)
JPS6311799U (en)
JPS63161499U (en)
JPH0366242U (en)
JPH02108102U (en)
JPS62198738U (en)
JPH0197635U (en)
JPS62121652U (en)
JPH0255346U (en)
JPH0163224U (en)
JPS60174947U (en) input/output control device
JPS6142588U (en) memory control circuit
JPS6251428U (en)
JPS6454661U (en)
JPS61116436U (en)
JPS61197778U (en)
JPS6457548U (en)
JPS6266329U (en)
JPS62195863U (en)
JPS6261544U (en)
JPH01120251U (en)
JPS62164422U (en)
JPS61196345U (en)
JPS61147449U (en)
JPS61113481U (en)