JPH056639Y2 - - Google Patents

Description

[Detailed explanation of the invention] <Technical field> This invention uses dynamic RAM as data memory.
Regarding the control device using
This article concerns a circuit that automatically refreshes RAM.

<Prior art> As a conventional control device of this type, for example, Z-
There is a computer that uses 80DMA. When using dynamic RAM as data memory in this computer, it is necessary to refresh the memory at predetermined intervals. However,
In the case of DMA, since there is no instruction fetch cycle, accesses are continuously repeated without refreshing. Therefore, if the input/output cycle continues for a long time, it is necessary to temporarily stop the DMA operation and insert a refresh cycle.

This results in a significant decrease in throughput and
You will not be able to take full advantage of the high speed that DMA has. Moreover, if the input/output device has a slow response speed, the input/output cycle becomes long, making it impossible to freely insert a refresh cycle, resulting in the problem that memory contents may be erased.

<Purpose of the invention> The present invention was devised in view of the above-mentioned problems, and it is possible to automatically refresh the dynamic RAM even during the DMA input/output cycle, thereby improving the performance of input/output devices with slow response speeds. The purpose is to allow DMA to directly access .

<Configuration of the invention> In order to achieve the above-mentioned object, the present invention has a dynamic RAM, an input/output request terminal that outputs an input/output request signal to an input/output device, and an M1 output that outputs an M1 signal. In a control device equipped with a DMA having a terminal,
Between the dynamic RAM and DMA, the
Only when the input/output request signal outputted from the input/output request terminal of the DMA is active and the M1 signal outputted from the M1 output terminal is inactive, a refresh signal is generated in response to the system clock. The dynamic RAM is refreshed during an input/output cycle based on a refresh signal output from the refresh circuit.

<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

FIG. 1 is a configuration diagram of a control device according to this embodiment. In the figure, numeral 1 is a control device, 2 is a dynamic RAM, 4 is a DMA, and 6 is a refresh circuit provided between the dynamic RAM 2 and DMA 4.

The DMA 4 includes a memory request terminal that outputs a memory request signal a to the dynamic RAM 2;
An input/output request terminal that outputs an input/output request signal c to an input/output device, a system clock b
The M1 output terminal M1 outputs an M1 signal e during a machine cycle. And each memory request terminal
MREQ, input/output request terminal, and M1 output terminal 1 have negative logic and are active at low level.

The dynamic RAM 2 also includes a refresh input terminal for inputting a refresh signal d and an input terminal for inputting a memory request signal a, and also incorporates a refresh address counter (not shown).

The refresh circuit 6 is a J flip-flop 8 in this example, and has three input terminals J, , .
One input terminal J of CK is set to high level together with the clear terminal CLR, the other input terminal is connected to the input/output request terminal of DMA4, and the clock input terminal CK is connected together with the clock input terminal Φ of DMA4. System clock terminal 1
0 in common. On the other hand, one of the two output terminals Q of the J flip-flop 8 is connected to the refresh input terminal of the dynamic RAM 2.

Next, the dynamic RAM 2 of this control device 1
The refresh operation will be explained with reference to the timing chart of FIG. here,
To explain the timing chart in FIG. 2, the A side direction is when an interrupt request is not being acknowledged, and the B side direction is when an interrupt request is being acknowledged.

Here, the interrupt request is being acknowledged.
A term commonly used for Z80DMA,
This means that the DMA4 requests an interrupt to the CPU, and the CPU grants the request.

When an interrupt request is not being acknowledged, the M1 signal e from the M1 output terminal 1 is at a high level, and when an interrupt request is being acknowledged, the M1 signal e from the M1 output terminal 1 of the DMA 4 is at a low level. Similarly, the input/output request signal c from the input/output request terminal of the DMA 4 is at a low level.

During this interrupt request acknowledgment,
Dynamic with self-refresh function
RAM2 is self-refreshed.

During the input/output cycle in which the DMA 4 accesses the input/output device, the memory request signal a output from the memory request terminal is always at a high level, so the input terminal of the dynamic RAM 2 is also kept at a high level. In this state, when the execution input/output address for reading and writing input/output data to the input/output device gets on the address bus, the input/output request signal c output from the input/output request terminal becomes low level, and therefore, Among the input terminals J of the J flip-flop 8, one input terminal J is set to a high level, and the other input terminal is set to a low level. Further, at this time, the M1 signal e output from the M1 output terminal 1 is at a high level, that is, inactive.

Therefore, every time the system clock b is input to the clock input terminal CK, the output terminal Q outputs a refresh signal d which repeats inversion in response to the rising timing of the system clock b.

Therefore, if the I/O device still cannot access DMA4 during the I/O cycle,
A wait cycle Tw is automatically inserted into the system clock b, and the refresh signal d is output from the J flip-flop 8 at this time as well.

This refresh signal d is then applied to the refresh input terminal of the dynamic RAM 2. Dynamic RAM2 is an input terminal
When the memory request signal a from DMA4, which is applied to RAS, is at a high level, the refresh input terminal
When the refresh signal d is input to RFSH, it becomes active and refreshes automatically every time the refresh signal d falls to low level, and the refresh address counter increments every time the refresh signal d rises to high level. be done. In this way, the dynamic RAM 2 is sequentially refreshed each time the input refresh signal d falls to a low level.

In the present invention, when the DMA 4 is not in the process of acknowledging an interrupt request, the dynamic RAM 2 is refreshed each time the refresh signal d given from the refresh circuit 6 falls to low level as described above. When it is inside, the second
DMA4 input/output request terminal as shown in the B side direction of the diagram
Both the input/output request signal c from IORQ and the M1 signal e from the M1 output terminal 1 become low level and are applied to the J flip-flop 8, and at this time, the J terminal of the J flip-flop 8 is always at a high level. Therefore, during this interrupt request acknowledgment, the refresh signal d from the J flip-flop 8 is held at a high level as shown in FIG. 2 and is not output, so that the refresh to the dynamic RAM 2 is stopped. .

Note that during this interrupt request acknowledgment, the dynamic RAM 2 is self-refreshed as described above.

<Effects of the invention> As described above, according to the invention, the dynamic
Between the RAM and DMA, only when the input/output request signal output from the input/output request terminal of the DMA is active and the M1 signal output from the M1 output terminal is non-active, A refresh circuit that outputs a refresh signal in response to the system clock is provided, and the dynamic RAM can be automatically refreshed during the input/output cycle based on the refresh signal output from the refresh circuit, resulting in faster response times. Even for slow input/output devices, a refresh signal can be generated without adding an extra load to the DMA, and since no refresh signal is output during interrupt request acknowledgment when self-refresh is performed, dynamic RAM Refreshing can be performed optimally, and the application range for input/output devices is expanded compared to the conventional method, which is an excellent effect.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a control device, and FIG. 2 is a timing chart for explaining the refresh operation of the device. 1...Control device, 2...Dynamic RAM,
4...DMA, 6...Refresh circuit.

Claims (1)

[Claims for Utility Model Registration] A control device equipped with a dynamic RAM and a DMA having an input/output request terminal that outputs an input/output request signal to an input/output device and an M1 output terminal that outputs an M1 signal. In this case, there is a connection between the dynamic RAM and the DMA.
Only when the input/output request signal outputted from the input/output request terminal of the DMA is active and the M1 signal outputted from the M1 output terminal is inactive, a refresh signal is generated in response to the system clock. What is claimed is: 1. A control device comprising: a refresh circuit that outputs a refresh signal; and refreshes the dynamic RAM during an input/output cycle based on a refresh signal output from the refresh circuit.