JPH0253291A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To accelerate the processing speed of a system by comparing a refresh address outputted from a refresh address counter with a row address inputted from the outside at the time of making access, and outputting a coincidence signal to the outside when they coincide. CONSTITUTION:The row address accessed at the time of making access from a CPU is fetched in the inside, and it is compared with the refresh address at a comparator 2, and when they coincide, the coincidence signal 8 is outputted to the outside. An out-fitted refresh interval timer is reset by the coincidence signal 8, and also, the refresh address counter 1 is advanced by one. In such a way, it is possible to eliminate the execution of wasteful refresh, and to reduce the number of times of interruption to the CPU, and to accelerate the processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device, and particularly to one equipped with a refresh address counter and a coincidence signal output circuit.

[Conventional technology]

Conventionally, this type of dynamic semiconductor memory device has a counter refresh function that performs refresh using a refresh address output from an internal refresh address counter without inputting a refresh address from the outside. It had an unknown structure.

[Problem to be solved by the invention]

Generally, in dynamic storage devices, refresh operations can be replaced by read/write operations.

Therefore, when refreshing is performed using the internal refresh address counter, if the address to be refreshed is accessed in a read/write operation, this address may be skipped without being refreshed. However, in the above-mentioned dynamic semiconductor memory device, the refresh address of the refresh address counter is generated completely asynchronously with the address accessed from the outside, so even addresses that can be skipped for the above-mentioned reasons are always refreshed. That is, there is a drawback that unnecessary refresh is executed and the processing speed of the CPU is reduced.

[Means to solve the problem]

The dynamic semiconductor memory device of the present invention compares a refresh address counter that is activated by an external refresh signal and generates a refresh address with a row address input from the outside at the time of access, and if they match, a match signal is sent. It has a match signal output circuit that outputs a match signal to the outside, and a refresh control circuit that executes refresh using a refresh address output from a refresh address counter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

1 is a refresh address counter which outputs the next address to be refreshed to the match signal output circuit 2 and the address buffer 3. The refresh control circuit 9 increments the value by 1 each time refresh is performed. 2 is a match signal output circuit that compares the refresh address output from the refresh address counter 1 with the row address input from the outside at the time of access and transmitted via the address buffer 5, and if they match, the output buffer 10 outputs the refresh address. A match signal 8 is output to the outside via. At this time, the match signal 8 is also output to the refresh control circuit 9. Reference numeral 3 denotes a refresh control circuit that executes a refresh operation in response to a refresh signal input from the outside.

After the refresh is completed, the refresh address counter 1 counts up the refresh address by 1. Furthermore, when the match signal 8 is received from the match signal output circuit 2, the refresh address of the refresh address counter 1 is counted up by 1.

Generally, when refreshing a dynamic semiconductor memory device by using a counter refresh cycle, an external refresh interval timer is provided. This refresh interval timer outputs a refresh request signal at preset fixed intervals. The refresh request signal arbitrates with the CPU access and then puts a wait on the CPU to refresh the dynamic semiconductor memory device.

In the dynamic semiconductor memory device of the present invention, an address (row address) accessed at the time of access from the CPU is internally stored and used as a refresh address and a comparison circuit 2.
A comparison is made and if a match is found, a match signal is output to the outside. By resetting the external refresh interval timer and incrementing the refresh address counter 1 by 1 using this match signal, it is possible to reduce the number of interrupts to the CPU without executing unnecessary refreshes, and improve processing speed.

That is, when the next address to be refreshed is accessed, the refresh of that address is skipped and no refresh is required for one refresh period from that point onward, thereby increasing the CPU access efficiency.

〔Effect of the invention〕

As explained above, the present invention compares the refresh address output from the refresh address counter with the row address input from the outside at the time of access, and if they match, ζ outputs a match signal to the outside, thereby eliminating unnecessary refresh. This has the effect of preventing problems and improving system processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Refresh address counter, 2...
... Match signal output circuit, 3 ... Address buffer, 4 ... Row decoder, 5 ...
Column decoder, 6...Sense amplifier, 7...
...Memory cell, 8... Match signal, 9...
. . . Refresh control circuit, 10 . . . Output buffer. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] A match signal output circuit that compares the refresh address output from the internal refresh address counter with the row address input from the outside at the time of access and outputs a match signal to the outside if they match, and a match signal output circuit that outputs a match signal to the outside when the refresh address is output from the internal refresh address counter. 1. A dynamic semiconductor memory device comprising a refresh control circuit that uses the refresh control circuit to perform refresh.