JPH0725920Y2 - Semiconductor memory device - Google Patents

Description

[Detailed Description of the Invention] [Industrial application] The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter referred to as DRAM) having a refresh address counter inside, in terms of system, external refresh, internal The present invention relates to a semiconductor memory device that can perform refresh operation without any trouble even if refresh is mixed.

[Conventional technology]

Conventionally, this type of semiconductor device has been required to perform a predetermined number of refresh operations within a certain fixed time. As the refresh method, a refresh address is given from the outside of the device for refreshing. ▼▼ External refresh by on-refresh, read, and write operations, and a refresh address counter is provided inside the DRAM chip inside the device and that address is used. Refresh ▼ Before Before ▲ ▼ Refresh,
There are two refresh methods, an internal refresh by a dedicated operation for refresh. However, the currently commercialized DRAM has a method of generating the address of the internal refresh counter regardless of the external refresh address.

[Problems to be solved by the invention]

The conventional two refresh methods, external refresh and internal refresh described above, are methods in which the address of the internal refresh counter is generated independently of the external refresh address. Therefore, the external refresh and the internal refresh cannot be mixed in the system. , For example, in the conventional ▲ ▼ before ▲ ▼ DRAM hidden refresh refresh, the refresh address and
There is a drawback that it is difficult to improve the efficiency of the refresh operation because it becomes irrelevant to the read address of one cycle before.

An object of the present invention is to provide a semiconductor memory device capable of external refreshing and improving refresh operation efficiency by simply adding a circuit to a DRAM having an internal refresh address counter.

[Means for solving problems]

A semiconductor memory device of the present invention is a write control for controlling writing of an address signal latched in an address buffer into a row address buffer and a column address buffer and a row selection signal and a column selection signal and input data to a memory cell. In a semiconductor memory device including at least a supply of an enable signal and including a dynamic random access memory having a refresh address counter therein, the row selection signal, the column selection signal or the write enable signal is received and externally input. A refresh address transfer control circuit that outputs a transfer signal that controls the transfer of an external refresh address to the refresh address counter, and the external refresh address by the control signal of the refresh address transfer control circuit. Address transfer gate that executes a gate operation without a response, and an address increment circuit that performs an addition operation when the gated external refresh address from the address transfer gate is input and transferred to the refresh address counter. .

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

In this figure, 101 is a ▲ ▼ clock generation circuit and 102 is a ▲
▼ clock generation circuit, 103 ▲ ▼ (write enable) clock generation circuit, 104 refresh control, 105 refresh address transfer control circuit, 106 refresh address counter, 107 address increment circuit, 108 address transfer gate, 1
09 is an address buffer, 110 is a row.ROW address buffer, 111 is a column address buffer, 112 is a memory cell array, row decoder and column decoder, 113 is an I / O switch and buffer, 114 is a data output (D _OUT ) Buffer, 115 is a data input (D _IN ) buffer.

FIG. 2 is a diagram showing the timing of refresh address transfer of the semiconductor memory device shown in FIG.

The operation of the semiconductor memory device of this embodiment will be described with reference to FIGS. 1 and 2.

First, the row address (A _{0 to} A ₇ ) is latched from the outside by falling the signal ▲ ▼ (see FIG. 2). At this time, the refresh address transfer control circuit 105 opens the address transfer gate 108 if the ▲ ▼ signal is at a high level (hereinafter referred to as "H") and the ▲ ▼ signal is at a low level (hereinafter referred to as "L"), The row address is fetched, the address is incremented by one by the address increment circuit 107, and then set in the refresh address counter. The detected signal input to the refresh address transfer control circuit 105 is ▲ ▼
Signals other than signals, such as ▲ ▼ signals or ▲
▼ It may be a signal. Further, the address increment operation need not be limited to advancing by one address.

By the one cycle shown in FIG. 2, the refreshing of the memory cell designated by the row address is completed, and the address obtained by advancing the row address by one address is set in the refresh address counter 106. For the next refresh for this purpose, the internal refresh can be executed using the value of the refresh address counter 106. When it is desired to change the internal refresh address, the internal refresh address can be set using the cycle shown in FIG.

FIG. 3 shows a read cycle, a refresh address transfer cycle, and ▲ in the semiconductor memory device of the present invention.
▼ Before ▲ ▼ It is a timing chart when a refresh cycle and a re-read cycle are continuously performed. The row address i is read in the first read cycle, and the memory cells in the i-th row are refreshed. In the next refresh address transfer cycle, the row address j is read, the memory cells in the jth row are refreshed, and (j + 1) is set in the refresh address counter at the same time. Next, in the before-refresh cycle, the row address is not read and the memory cell of the (j + 1) th row set in the refresh address counter is refreshed. In the next read cycle,
The row address K is read and the memory cells in the K row are refreshed.

Executed during the read cycle as described above
Before-Refresh The refresh address for refreshing is controlled by an external address, so that refreshing by an external address and refreshing by an internal address can be mixed. Also, internal refresh is ▲
▼ Before ▲ ▼ Not limited to refresh, it can be applied to other internal refresh methods. The read cycle shown in FIG.
▼ A refresh cycle is acceptable.

[Effect of device]

As described above, according to the present invention, in the DRAM having the refresh address counter therein, the refresh address transfer control circuit, the address increment circuit, and the address transfer gate are provided so that the external refresh and the internal refresh can be mixed in the system. Therefore, there is an effect that the efficiency of the refresh operation can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a refresh address transfer timing chart of the semiconductor memory device shown in FIG. 1, and FIG. 3 is a semiconductor memory device shown in FIG. It is a time chart of refresh operation. 101 ... ▲ ▼ Clock generation circuit, 102 ... ▲ ▼ Clock generation circuit, 103 ... ▼ Clock generation circuit, 104 ...
Refresh control, 105 ... Refresh address transfer control circuit, 106 ... Refresh counter, 107 ... Address increment circuit, 108 ... Address transfer gate, 109 ... Address buffer, 110 ... Row address buffer, 111 ... Column address buffer, 112 ... Memory cell array, Row decoder and column decoder, 11
3 ... I / O switch buffer, 114 ... D _OUT buffer, 115 ...
D _IN buffer.

Claims (1)

[Scope of utility model registration request] 1. A row select signal and a column select signal for controlling latching of an address signal latched in an address buffer to a row address buffer and a column address buffer, and a write enable signal for controlling writing of input data to a memory cell. Of a dynamic random access memory having a refresh address counter inside, and an external refresh address externally input in response to the row selection signal, the column selection signal or the write enable signal. A refresh address transfer control circuit for outputting a transfer signal for controlling the transfer to the refresh address counter, and a gate of the external refresh address by a control signal of the refresh address transfer control circuit. A semiconductor having an address transfer gate for executing an operation and an address increment circuit for performing an addition operation when the gated external refresh address from the address transfer gate is input and transferred to the refresh address counter. Storage device.