JP2767242B2 - Refresh control method for D-RAM - Google Patents

Description

The present invention relates to a dynamic memory (hereinafter referred to as a D-RAM).
In particular, there is no instruction having a program wait (WAIT, wait), halt (halt, pause), long execution time, etc. (Hereinafter referred to as CPU), read-only memory (hereinafter referred to as ROM), I / O
The number of accesses to devices other than D-RAM such as
The present invention relates to a refresh control method for a D-RAM used in a control system such as a high-speed recording device, a robot, and a data collector, which has a number of addresses of the D-RAM required for refreshing. [Prior Art] In a D-RAM composed of MOS transistors, a charge is accumulated using the stray capacity of a gate, so that the charge disappears with time due to a leak current or the like. For this reason, in a control system incorporating the D-RAM, a so-called refresh process in which a clock pulse is periodically applied within a predetermined time to release electric charges is required. As a control circuit for performing such a refresh, a counter circuit for generally receiving a refresh request signal formed based on a set time of a timer circuit and counting up is provided, and the address signal is sequentially circulated by the counter circuit for a predetermined time. There is an apparatus which forcibly transmits the data to the D-RAM side every time and refreshes the data. "Problems to be Solved by the Invention" However, if a configuration in which the address signal is periodically transmitted at predetermined time intervals while the counter value is updated is adopted as described above, the refresh cycle may be 2 to 2 in consideration of a worst case. Since a very short refresh cycle of about 4 msec is selected, in a system that performs frequent read / write operations such as a control system for a high-speed recording apparatus, the D-D
There was a problem that it became difficult to use RAM as memory. In order to solve such disadvantages, for example, Japanese Patent Application Laid-Open No. 61-190794
As disclosed in JP-A-61-34791, for example, a read / write signal is transmitted to a specific address of the D-RAM. While a region is being accessed, a technique has been proposed in which another address region of the D-RAM is forcibly refreshed based on a timing signal generated by a timer or other timing generation circuit. In any of these conventional techniques, not only a timer circuit or a similar timing generation circuit is required, but also in the former, a control circuit that varies the set time of the timer circuit based on stored information, and in the latter, a refresh signal is generated. There is a problem that a circuit for adjusting the address area is required, and the circuit configuration is complicated. The present invention has been made in view of the above-described drawbacks of the related art, and in a specific control system, various types of address information transmitted from a CPU without the need for the timer circuit or a similar timing generation circuit and a complicated control circuit. It is an object of the present invention to provide a D-RAM refresh control system capable of performing the refresh operation with an extremely simple circuit configuration by effectively utilizing the above. "Means for solving the problems" Generally, control of PROM or MASKROM which stores a control program or data transmitted from the CPU, a sensor or an output device, a laser printer composed of a D-RAM as an image memory, etc. In the system, the refresh cycle time of the D-RAM, for example, 2 to 8
Within msec, the number of accesses between the CPU and devices other than the D-RAM, such as the ROM and the I / O device, is equal to or more than the number of addresses of the D-RAM required for refresh, specifically, for refresh. It is already clear that there are at least several times the number of addresses, and when the CPU accesses each of the above devices, the address signal transmitted from the CPU is limited only to the ROM or I / O device to be accessed. This is a valid signal, and is meaningless information for other devices such as a D-RAM. Therefore, at least one device other than the D-RAM
Sending the refresh address signal to the D-RAM while the PU is accessing does not cause any problem. Therefore, the present invention provides a D having the following two essential processing steps.
-Propose a refresh control method for RAM. When the CPU is accessing the device other than the D-RAM, the refresh address signal in the counter is supplied to the D-RA.
A first processing step of transmitting to the M side and performing a refresh processing, and the first processing step includes, for example, a signal ROMSEL for selecting the device other than the D-RAM1 as shown in FIG.
The first feature is that the refresh processing step is configured to transmit the refresh address signal C + n from the counter 6 to the D-RAM 1 when the output timing of the address strobe signal transmitted from the CPU and the CPU coincides with each other. . As a result, the refresh operation can be performed only by the AND gate circuit 4 and the counter 6 without using a timer or other timing generating circuit and without providing a special control circuit for adjusting the timing as in the prior art. And the circuit configuration is extremely simplified. After the refresh processing is completed, before the next refresh processing is performed, a second processing step is provided in which the refresh address in the counter is updated in a circulating manner, and the second processing step comprises: As shown in FIG.
The n-updating is performed in the counter 6 by using the rising trigger of the output signal of the AND gate circuit 4 that occurs when the refresh processing is completed and the address strobe signal AS or the select signal ROMSEL is no longer received. A second feature is that the refresh address is configured to be updated in a circulating manner. Also in such a processing step, no special circuit configuration other than the AND gate circuit 4 and the counter 6 is required, and the circuit configuration is extremely simplified. According to the control method of the present invention, the output cycle of the select signal ROMSEL, in other words, the number of accesses between the CPU and at least one or more devices other than the D-RAM1 depends on the address of the D-RAM1 required for refreshing. Since it is premised on using the control system having the number n, in other words, the number n of address information in the counter 6 to be updated in a cyclic manner, all the addresses C to C within the refresh cycle time of the D-RAM are required. There is no possibility that C + n is not refreshed, and smooth refresh processing can be performed. Further, since the refresh processing is not performed during the access between the CPU and the D-RAM1, there is no problem in performing the read / write of the D-RAM1. Hereinafter, preferred embodiments of the present invention will be illustratively described in detail with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely illustrative examples. It's just FIG. 1 shows the D built into the controller of the laser printer.
A block diagram showing a refresh control circuit of the RAM, FIG.
FIG. 3 and FIG. 3 are a flowchart and a time chart thereof. In FIG. 1, reference numeral 1 denotes a D-RAM used as an image memory, in which memory cells in the form of an XY matrix are incorporated. (Note that an address in the X direction of the memory cell is defined as a column address and an address in the Y direction is defined as a row address.) 2 is a row address signal transmitted from the CPU based on the column / row switching timing signal COL / ROW. A and a multiplexer for transmitting the A and column address signal B to the D-RAM side in a time-division manner (see time chart,...).
This is a second multiplexer for transmitting the refresh address signal C + n in the counter 6 to the D-RAM 1 via the multiplexer 2 based on the ROM select signal ROMSEL transmitted from U. (Time chart diagram,
4) When the ROM select signal ROMSEL is transmitted, the address strobe signal AS of the D-RAM 1 transmitted from the CPU is transmitted to the counter 6 side, and the refresh address signal C + n in the counter 6 is transmitted to the multiplexer 2. D through 3,
-While transmitting to RAM1 to perform refresh processing,
After completion of the refresh processing, the address strobe signal AS
And an update circuit for updating the refresh address C + n in the counter 6 in a circulating manner by using a rising trigger of the output signal of the AND gate circuit 4 which is generated when any of the signals of the ROM select signal ROMSEL is not received. It is. (See FIG. 3,...) Reference numeral 5 denotes an AND circuit that transmits a column address signal B to the D-RAM1 based on the DRAM select signal DRAMSEL and the column address strobe timing signal CAS. (Refer to FIG. 3) The operation procedure of the control circuit will be described below with reference to FIGS. 2 and 3. First, in the control system according to the present embodiment, the D-RA
M select signal DRAMSEL and ROM select signal ROMSEL
The cycle is transmitted alternately and continuously from the side, and the periodic cycle thereof is at least several times the refresh address number n circulated by the counter 6 within the refresh cycle time of the D-RAM 1, for example, 2 to 8 msec. . Also, address strobe AS, column / row switching timing signal COL /
The ROW and column address strobe signals CAS are also transmitted continuously in synchronization with the periodic cycle. (Fig. 3,
Under such preconditions, as shown in the left column of FIG. 2, during the D-RAM select cycle, the column / row switching timing signal COL / RO input to the multiplexer 2 is supplied.
It is determined whether W is a timing of a column or a row. In the case of a column timing, a column address signal B on the CPU side, and in the case of a row timing, a row address signal A,
The data is transmitted to the D-RAM in a time-division manner, and image data is written and read into and from the memory cells in the D-RAM based on the read / write signal R / W transmitted to the D-RAM. Also, as shown in the right column of FIG. 2, in the case of a ROM select cycle, it is determined whether or not the column / row switching timing signal COL / ROW input to the multiplexer 3 is a row timing. The refresh address signal C + n in the counter 6 is transmitted to the D-RAM 1 via the multiplexers 2 and 3 based on the request request signal of the AND gate circuit 4 to perform refresh processing. After the refresh is completed, the address strobe signal AS
Using the rising trigger of the output signal of the AND gate circuit 4 that occurs when any one of the ROM select signal ROMSEL and the ROM select signal ROMSEL is not received, the refresh address in the counter 6 is updated in a circulating manner. When the column / row switching timing signal COL / ROW is a column timing, the CPU transmits a column address signal B on the CPU side to the D-RAM side. In this state, the CPU and the D-RAM1 are in non-access information. Then, it becomes meaningless information. Similarly, the row address signal A transmitted to the D-RAM between the D-RAM select cycle and the ROM select cycle is also meaningless. [Effects of the Invention] As described above, according to the present invention, a timer or other timing generation circuit or a special control circuit can be effectively used by effectively using an access cycle between at least one device other than a D-RAM and a CPU. , A refresh operation can be performed with a simple circuit configuration. Further, according to the present invention, there is no possibility that all predetermined addresses are not refreshed within the refresh cycle time of the D-RAM, and smooth refresh processing can be performed. Further, since the refresh processing is not performed during access between the CPU and the D-RAM, there is no problem in performing read / write of the D-RAM. And so on.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 3 show an embodiment of the present invention. FIG. 1 shows a D-RA incorporated in a controller of a laser printer.
2 and 3 are a flowchart and a time chart, respectively, showing the M refresh control circuit. 1: DRAM, 2,3: Mux, 4,5: And circuit, 6: Counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/406

Claims (1)

(57) [Claims] Within the refresh cycle time of the D-RAM, the D-R
The number of times the CPU accesses at least one device other than AM is the number of D-RAMs required for refresh.
Embedded in a control system with more than the number of addresses
In the RAM refresh control method, when the CPU is accessing the device other than the D-RAM, the refresh address signal in the counter is transmitted to the D-RAM.
A first processing step of transmitting the refresh processing to the side and performing a refresh processing, and a second processing in which the refresh address in the counter is updated in a circulating manner after the refresh processing and before the next refresh processing is performed. The first processing step includes refreshing the counter to the D-RAM side when the output timing of the signal ROMSEL for selecting the device other than the D-RAM and the address strobe signal transmitted from the CPU coincides with each other. A refresh processing step of transmitting an address signal; and the second processing step includes an AND gate circuit which is generated when one of the address strobe signal and the select signal is not received after the refresh processing is completed. Use the rising trigger of the output signal to circulate the refresh address in the counter. D-RAM refresh control method and wherein the form is a processing step of performing an address update in said counter