JP2908485B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial application field Conventional technology (FIGS. 4 and 5A to F) Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiment ( (FIGS. 1, 2A-G, FIG. 3) Configuration of one embodiment Operation of one embodiment Effects of one embodiment Effects of the invention [Summary] A semiconductor memory device adopting an address multiplex system for an address input system. , For example, dynamic
The purpose of RAM is to reduce the number of external control signals and reduce the timing regulation between external control signals. The signals ▲ ▼ and ▲ ▼ are combined into one-phase signals, and the signals ▲ ▼ and ▲ ▼ Are integrated into another one-phase signal so that the conventional operation mode can be executed.

[Industrial Application Field] The present invention relates to a semiconductor memory device adopting an address multiplexing method (address multiplexing), for example, a dynamic RAM (hereinafter, DRAM).
About).

In such a semiconductor memory device, a ▲ ▼ (row address strobe) signal, ▲
▼ (oclumn address strobe) signal, ▲ ▼ (write e
nable) signal and ▲ ▼ (output enable) signal.

[Prior Art] Conventionally, as an address input method, a semiconductor memory device adopting an address multiplex method, for example, a DRMA whose main part is shown in FIG. 4 has been proposed as a DRMA.

In the figure, 1 is a memory cell array, 2 is a row address buffer, 3 is a row decoder, 4 is an address counter, 5 is a column address buffer, 6 is a column decoder, and 7 is an I / O
An O gate, 8 is a sense amplifier, 9 is an input buffer, and 10 is an output buffer.

Reference numeral 11 denotes a first clock generator. The first clock generator 11 receives a supply of a signal and outputs a first clock signal. The first clock signal is supplied to a row address buffer 2, a row decoder 3, a sense amplifier 8, an output buffer 10, and a write clock generator 17 described later.

12 is a delay circuit, 13 is a second clock generator, 14 is an ATD (address transi-tion detector) activation signal generation circuit, 15 is an ATD circuit, and 16 is a CLS (column line se
lect) A gate control signal / BLL (bus line latch) signal generation circuit, and 17 is a write clock generator.

The delay circuit 12 delays the first clock signal generated by the first clock generator 11 and supplies it to the second clock generator 13. Also, the second clock generator 13 outputs a second clock signal,
This is supplied to the column address buffer 5, the ATD activation signal generation circuit 14, and the write clock generator 17.

The ATD activation signal generation circuit 14 outputs an ATD activation signal, supplies the ATD activation signal to the ATD circuit 15, and activates the ATD circuit 15, and the ADT circuit 15 outputs an ATD signal. This is supplied to the CLS gate control signal / BLL signal generation circuit 16.

Also, the CLS gate control signal / BLL signal generation circuit 16
A gate control signal and a BLL signal are output. Of these, the CLS gate control signal is supplied to the column decoder 6,
The column decoder 6 generates an LCS signal, supplies the BLL signal to the output buffer 10, and latches the data appearing on the bus line in the output buffer 10.

In addition, the write clock generator 17 outputs the first clock signal, the second clock signal,
▼ A signal is supplied to output a write clock signal, which is supplied to the input buffer 9 so that the input buffer 9 can latch data supplied from the outside.

Reference numeral 18 denotes a CBR (▲ before ▲) signal generation circuit, which receives the ▲ ▼ signal and the ▲ ▼ signal, outputs a CBR signal, and outputs the CBR signal to the ATD activation signal generation circuit 14 and the row address. The data is supplied to the buffer 2 and the address counter 4. This CBR signal is used when executing the below-mentioned ▼, before, ▲, and refresh modes.

In such a conventional DRAM, as an operation mode, a normal read mode (a mode simply called a read mode, in which data is read from a memory cell, as shown in time charts in FIGS. 5A to 5F, respectively). Read mode (see FIG. 5A), normal write
Mode (a mode simply called a write mode, in which data is written to a memory cell).
Ｂ, only refresh mode (mode in which refresh is performed by performing only reading and rewriting of a specified row; see FIG. 5C), read-modify-write mode (This mode is also called a read / write mode, which is a combination of the normal read mode and the normal write mode. See FIG. 5D), ▲ ▼ ・ Before ・ ▲ ▼ ・ Refresh mode (address A refresh mode in which a refresh address is generated internally using the counter 4. See FIG. 5E), a hidden refresh mode (data output in the read mode is held in the output buffer 10, and ▲ ▼ ・ Before ・ ▲
▼ ・ Mode to execute refresh mode. FIG. 5F
6) can be executed.

[Problem to be Solved by the Invention] However, in the DRAM of FIG. 4 of the related art, in order to execute the above-described various modes, four signals of ▲ ▼ signal, ▲ ▼ signal, ▲ ▼ signal and ▲ ▼ signal are required.
Therefore, it is necessary to set necessary timings between these four external control signals.
For this reason, there is a problem that a considerable amount of regulation is required only for the timing regulation for writing and reading.

In view of the above, it is an object of the present invention to reduce the number of external control signals and to reduce the timing regulation between external control signals, in a semiconductor memory device employing an address multiplexing method such as a DRAM.

[Means for Solving the Problems] In the semiconductor memory device of the present invention, first and second logic signals are used as external control signals. Then, for the first logic signal, a first logic state change (for example, a logic state change from "L" to "H" in one cycle.
Same. ) And a second logic state change (eg, "H" to "L")
Logic state change to. The same applies hereinafter. ) Are sequentially performed (Example drawings FIGS. 2A to 2G, S1 and S2 in FIG. 3).
reference).

Further, a logic state detecting means for detecting the logic states of the first and second logic signals is further provided inside the chip, so that the following operation can be performed.

(1) When it is detected that the second logic signal is in one logic state (for example, “H”; the same applies hereinafter) when the first logic signal changes the first logic state, The data of the memory cell is transmitted to and held in the output buffer, and thereafter, when the first logic signal changes the second logic state, the second logic signal changes to the other logic state (for example, “L”). (Hereinafter the same), the data held in the output buffer is output to the outside (see FIG. 2A).

(2) On the other hand, when a predetermined time elapses after the first logic signal has changed the first logic state, and when it is detected that the second logic signal has changed to the other logic state, an input is performed. When data is fetched into the buffer, and then when the first logic signal changes to the second logic state, and when the second logic signal is detected to be in one of the logic states, it is input to the input buffer. The stored data is written into the memory cells (see FIG. 2B).

In a configuration in which the above operation can be performed, a normal read mode, a normal write mode, an S1 only refresh mode (a mode corresponding to the conventional ▲ ▼ only refresh mode) ) Can be executed (see FIGS. 2A to 2C).

After a lapse of a predetermined time from the time when the first logic signal changes the first logic state, the second logic signal changes to the other logic state, and thereafter, the logic state of the second logic signal changes. Does not change, when the first logic signal changes to the first logic state, and when it is detected that the second logic signal is in the other logic state, the data held in the output buffer is When the data held in the input buffer can be written to the memory cell after the reading, in addition to the above modes, a read-modify-write mode is executed. (See FIG. 2D).

Further, when the first logic signal changes to the first logic state and when the second logic signal detects that the other logic state is in the other logic state, the row address is selected by the internal circuit. Can be configured. In this case, in addition to the above-mentioned, in addition to S2, before, S1, refresh mode (conventional ▲ ▼, before, ▲ ▼
A refresh mode) and a hidden refresh mode (see FIGS. 2F and 2G).

[Operation] In the present invention, the above-mentioned mode can be executed by setting the timing relationship between the first logic signal and the second logic signal as follows.

(1) Normal read mode (see FIG. 2A) When executing this mode, when the first logic signal changes the first logic state, the second logic signal changes to one logic state. And after the predetermined time has passed, before the first logic signal makes the second logic state change, the second logic signal is set to the other logic state, whereby the first logic signal is When making the second logic state change, the second logic signal is in the other logic state.

In this case, when the first logic signal changes the first logic state, it is detected that the second logic signal is in one logic state, so that the data of the memory cell is transmitted to the output buffer. Being held. Thereafter, when a predetermined time has elapsed, the second logic signal does not change to the other logic state, but changes to the other logic state after the predetermined time has elapsed. Therefore, the operation for writing is not performed.

Then, in this example, the first logic signal is then changed to the second logic signal.
Is performed, the second logic signal is detected to be in the other logic state, so that the data held in the output buffer is output to the outside.

Thus, the normal read mode is executed.

(2) Normal write mode (see FIG. 2B) When executing this mode, when the first logic signal changes the first logic state, the second logic signal changes to one logic state. After the predetermined time has elapsed, the second logic signal is set to the other logic state, and then the second logic signal is changed to the second logic state before the first logic signal changes to the second logic state. Return the signal to one logic state.

In this case, when the first logic signal changes the first logic state, it is detected that the second logic signal is in one logic state, so that the data of the memory cell is transmitted to the output buffer. After a predetermined time has elapsed, the second logic signal goes to the other logic state, which is detected, so that data supplied from the outside is taken into the input buffer. After that, when the first logic signal changes to the second logic state, it is detected that the second logic signal is in one of the logic states. Is written to.

Thus, the normal write mode is executed.

(3) S1 only refresh mode (Fig. 2C
When performing this mode, the second logic signal is maintained in one logic state while the first logic signal changes the first and second logic states.

In this case, when the first logic signal changes the first logic state, it is detected that the second logic signal is in one logic state, so that the data of the memory cell is transmitted to the output buffer. Being held. Thereafter, when a predetermined time elapses, the second logic signal does not enter the other logic state, so that external data is not taken into the input buffer, and the first logic signal is changed to the second logic signal. When the state changes, the second logic signal is detected to be in one of the logic states, so that the data held in the output buffer is not output to the outside. However, since the transmission of the data to the output buffer has been performed, the memory cell is refreshed.

Thus, the S1-only refresh mode is executed.

(4) Read-modify-write mode (see FIG. 2D) When this mode is executed, when the first logic signal changes the first logic state, the second logic signal becomes one of the two. The second logic signal is changed to the other logic state when a predetermined time has elapsed, and then maintained at the other logic state, and when the first logic signal changes the second logic state. , In the other logic state.

In this case, when the first logic signal changes the first logic state, it is detected that the second logic signal is in one logic state, so that the data of the memory cell is transmitted to the output buffer. Being held. Further, when a predetermined time has elapsed, the second logic signal becomes the other logic state, and this is detected, so that data supplied from the outside is taken into the input buffer. Thereafter, when the first logic signal changes to the second logic state, it is detected that the second logic signal is in the other logic state, so that the data fetched into the input buffer is stored in the memory cell. Written.

Thus, the read-modify-write mode is executed.

(5) S2 before S1 refresh mode (second
When performing this mode, when the first logic signal makes a first logic state change, the second logic signal is in the other logic state.

With this configuration, when the first logic signal changes the first logic state, it is detected that the second logic signal is in the other logic state, so that the row address is selected by the internal circuit. . Here, an S2-before-S1 refresh mode can be executed.

(6) Hidden refresh mode (see FIGS. 2F and 2G) The next cycle of read mode is S2, before, S1,
Since the refresh mode can be set, the hidden refresh mode can be executed in this manner (see FIG. 2F).

Since the next cycle of the read / write mode can be set to the S2-before-S1 refresh mode, the hidden refresh mode can be executed in this manner (FIG. 2G). reference).

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1 to FIG.
This embodiment is a case where the present invention is applied to a DRAM.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.
2A to 2G are time charts showing various operation modes of one embodiment of the present invention. In this embodiment, FIG. 2A shows first and second logic signals as external control signals.
To G (hereinafter simply referred to as S1 and S2).
Is used.

Here, in FIG. 1, reference numeral 20 denotes a memory cell array, 21
Is a row address buffer, 22 is a row decoder, 23 is an address counter, 24 is a column address buffer, 25 is a column decoder, 26 is an I / O gate, and 27 is a sense amplifier. It is configured similarly to.

Reference numeral 28 denotes an input buffer and 29 denotes an output buffer.
enable) signal to latch data supplied from the outside, and a write operation can be performed by a WDR (write driver) signal. The output buffer 29 is configured to output data by an OPE (output enable) signal.

30 is a first S1 delay circuit, and 31 is an RLS (row line se
lect) signal, CAE (column address enable) signal, ▲
▼ (row adderess latch) signal / SAL (sense amp l)
atch) signal generation circuit, 32 is RLS ・ CAE ・ ▲ ▼ ・ SAL
This is a reset signal generation circuit.

Here, the first S1 delay circuit 30 delays S1 for a predetermined time and supplies the same to the RLS signal / CAE signal / ▲ ▼ signal / SAL signal generation circuit 31. Also, the RLS signal C
The AE signal, ▲ ▼ signal, and SAL signal generation circuit 31 outputs the RLS signal, CAE signal, ▲ ▼, and SAL signals as shown in FIG. 3, E, D, C, and F in response to the delayed S1. Is what you do. Further, the RLS / CAE / ・ / SAL reset signal generation circuit 32 is provided for the RLS / CAE / ▲ / SAL signal generation circuit 31 with respect to the RLS / CAE / ▲ / SAL signal generation circuit 31.
・ SAL reset signal is supplied, RLS signal, CAE signal, ▲
The signal and the SAL signal are reset.

The RLS signal is supplied to the row decoder 22, which activates the row decoder 22 to select a word line. The CAE signal is supplied to the column address buffer 24,
It controls the reception of column addresses. Also, ▲
▼ The signal is supplied to the row address buffer 21, and the input of the row address to the row address buffer 21 is inhibited in response to the column address buffer 24 entering the column address receivable state in response to the CAE signal. The row address buffer 21 is latched. The SAL signal is a signal obtained by delaying the RLS signal, is supplied to the sense amplifier 26, drives the sense amplifier 26, and is supplied to the ATD activation signal generation circuit 33.
This is driven to generate an ATD activation signal.

Reference numeral 34 denotes an ATD circuit, and reference numeral 35 denotes a CLS gate control signal / BLL signal generation circuit, which are configured in the same manner as the conventional example shown in FIG.

Reference numeral 36 denotes an OPE signal generation circuit, and 37 denotes an OPE signal delay circuit. The OPE signal generation circuit 36 receives the supply of S1 and S2, outputs an OPE signal, and outputs the OPE signal to the output buffer 29 and the OPE signal. This is supplied to the delay circuit 37. Also, OPE
The signal delay circuit 37 delays the OPE signal.

38 is a ▲ ▼ signal generation circuit, 39 is a WDR signal generation circuit, 40 is a ▼▼ reset signal generation circuit, and ▲ ▼ signal generation circuit 38 is a first S1 delay signal and
It receives the supply of S2 and outputs a ▲ ▼ signal. Also, the WDR signal generation circuit 39 outputs the ▲ ▼ signal and the OPE
Upon receiving the supply of the delay signal, it outputs a WDR signal and supplies it to the input buffer 28. The reset signal generating circuit 40 receives the signal and the WDR signal, outputs a reset signal, and supplies the reset signal to the signal generating circuit 38.

Reference numeral 41 denotes an S2BS1 (S2 before S1) signal generation circuit, which is used when executing the S2 / before / S1 / refresh mode, as shown in FIG. 3P.
It generates the S2BS1 signal.

Reference numeral 42 denotes RLS / CAE when executing normal read mode, S1 only refresh mode, or the like.
A circuit for instructing the reset timing to the SAL reset signal generation circuit 32, which is provided with a second S1 delay circuit 43, an inverter 44, and a NOR circuit 45. .

Operation of one embodiment (see FIGS. 2 and 3) I. Normal read mode (see FIGS. 2A and 3) (1) When S1 becomes "H" (FIG. 3A), After a predetermined time delay, the RLS signal is generated, and the word line selecting operation is started (FIG. 3E), the CAE signal is generated, and the column address is accepted (FIG. 3D). , ▲ ▼
A signal is generated and latched so that input to the row address buffer 21 is inhibited (FIG. 3C). Also,
When the SAL signal is generated, the sense amplifier 27 is driven to amplify the data of the memory cell oozing into each column (third).
Figure F).

(2) The generation of the SAL signal drives the ATD activation signal generation circuit 33 and activates the ATD circuit 34 (FIG. 3H). The CLS signal is generated in the column data 25 (FIG. 3I), and the data appearing on the bus line is latched in the output buffer 29 by the BLL signal (FIGS. 3J and O).

(3) After that, when S1 changes to “L” and S2 is detected to be “L”, the data latched in the output buffer 29 is output by the generation of the OPE signal (No. 3 K, M).

(4) When S1 becomes "L" and this is delayed for a predetermined time by the second S1 delay circuit 43, the output of the NOR circuit 45 becomes "H" and RLS ・ CAE ・ ▲ ▼ ・ SAL The reset signal generating circuit 32 is activated, and the CAE signal / RLS signal is reset (FIGS. 3D and 3E).

(5) The reset of the CAE signal releases the ▲ ▼ signal (FIG. 3C), the reset of the RLS signal releases the SAL signal (FIG. 3F), and resets the ATD activation signal generation circuit 33. And the ATD circuit 34 is deactivated (FIG. 3H). When the ATD circuit 34 is deactivated, the CLS signal is reset (FIG. 3I) and the BLL signal is released (FIG. 3J).

The normal read mode is executed as described above.

II. Normal write mode (see FIGS. 2B and 3) (1) Output of the first S1 delay circuit 30 in parallel with execution of (1)-of the normal read mode When S2 changes to "L" when the signal becomes "L" (broken line in FIG. 3B), a signal is generated, the input buffer 28 is activated, and the data supplied from the outside is latched. (FIG. 3L).

(2) After the normal read mode (2)-is performed, when S1 changes to "L" and S2 is detected to be "H", a WDR signal is generated ( (Fig. 3N),
A bus line is forcibly set according to the data taken into the input buffer 29, and data is written by transmitting data to a predetermined column.

(3) After the rise of the WDR signal, the operation of the reset signal generation circuit 40 resets the signal generation circuit 38 (FIG. 3L), and also resets the WDR signal generation circuit 39 as a flow. (FIG. 3N).

(4) Normal reset is performed by resetting the WDR signal.
Modes (4) and (5)-are executed.

The normal write mode is executed as described above.

III. S1 only refresh mode (Fig. 2C,
(Refer to FIG. 3.) (1) An operation of rewriting a memory cell by using (1)-of the normal read mode, but usually up to (2)-of the normal read mode. Circuit operation is performed.

(2) The CAS signal and the RLS signal are reset in a state where S1 is "L" and S2 is "H" and no signal is generated.

(3) Then, in normal read mode (5)-
Is performed.

As described above, the S1-only refresh mode is executed.

IV. Read-modify-write mode (See Fig. 2D and Fig. 3) (1) Normal read mode and normal write mode
In the combined mode, first, the normal write mode (1)-is performed.

(2) Then, in normal read mode (2)-
And (3) are performed.

(3) Then, after the lapse of the time of the OPE signal delay circuit 37 after the generation of the OPE signal, the WDR signal generation circuit 39 is driven, and
Write mode (2)--, (3)--,
(4) is continued.

As described above, the read-modify-write
The mode is executed.

V.S2 Before S1 Refresh Mode (See FIGS. 2E and 3) (1) When S1 becomes “H”, if S2 is “L”, S2B1
The signal generation circuit 41 is driven (FIG. 3P), and the address signal from the address counter 23 is supplied to the row address buffer 21.
Is switched to be input to.

(2) Thereafter, based on the address signal input to the row address buffer 21, rewriting to the memory cell is performed in the same manner as in the S1 only refresh mode.

As described above, the S2 / before / S1 refresh code is executed.

VI. Hidden refresh mode (see FIGS. 2F, 2G, and 3) This mode can be performed by the following two operations.

VI-1. The data output in the normal read mode is retained by setting S2 to “L”, and the S2 before S1 refresh mode is executed in the next cycle (No. 2 Figure F).

VI-2. Data output in read-modify-write mode is retained by setting S2 to “L”, and in the next cycle, S2 before S1 refresh mode is executed. (FIG. 2G).

Effects of One Embodiment As described above, according to this embodiment, as in the case of the conventional example shown in FIG. 4, the normal read mode, the normal write mode, the S1 only refresh mode, the read mode Modify write mode, S2
Six modes of before S1 refresh mode and hidden refresh mode can be executed, but the required external control signal is two logic signals S1
And S2 are sufficient, as in the conventional example of FIG.
▲ ▼ signal, ▲ ▼ signal, ▲ ▼ signal 4
No external control signals are required. Therefore, the timing regulation of the external control signal can be reduced.

It should be noted that the present invention is applicable to the case where S1 is as shown in FIG. 2 and S2 is opposite to the case shown in FIG. 2 as long as the logical states of S1 and S2 have the timing shown in FIG. 2 is opposite to the case shown in FIG. 2, and when S2 is as shown in FIG. 2, even when S1 and S2 are both opposite to the case of FIG. Can be obtained.

Further, in the above-described embodiment, the case where the present invention is applied to the DRAM is described. However, the present invention is also applicable to a semiconductor memory device employing an address multiplex system, for example, an SR.
It can be applied to AM.

[Effects of the Invention] According to the present invention, the following effects can be obtained.

That is, according to the first aspect of the present invention, a normal read mode, a normal write mode, and an S1-only refresh mode can be executed,
According to the second aspect of the present invention, a read-modify-write mode can be executed in addition to the above modes. According to the third aspect of the present invention, in addition to the above modes, furthermore, The S2, before, S1 refresh mode and the hidden refresh mode can be executed. In any case, two external control signals are sufficient. Timing regulation between external control signals can be reduced as compared with a semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of one embodiment (DRAM) of the present invention. FIGS. 2A to 2G are time charts showing operation modes of one embodiment of the present invention. FIG. 2B is a time chart showing a normal write mode, FIG. 2C is a time chart showing an S1-only refresh mode, FIG. 2D is a read modify FIG. 2E is a time chart showing an S2 before-S1 refresh mode, FIG. 2F is a time chart showing an example of a hidden refresh mode, FIG. 2G is a time chart showing an example of a hidden refresh mode. FIG. 3 is a time chart showing another example of the hidden refresh mode, FIG. 3 is a time chart showing various internal signals of one embodiment of the present invention, and FIG. 4 is an example of a conventional DRAM. 5A to 5F are time charts showing an operation mode of a conventional example, FIG. 5A is a time chart showing a normal read mode, and FIG. 5B is a normal chart.・ Time chart showing write mode, FIG. 5C is ▲ ▼ ・ Time chart showing only refresh mode, FIG. 5D is time chart showing read modify write mode, FIG. 5E is ▲ FIG. 5F is a time chart showing the hidden refresh mode. FIG. 5F is a time chart showing the hidden refresh mode. S1... First logic signal S2... Second logic signal

Claims (5)

(57) [Claims] 1. A semiconductor memory device employing an address multiplex system, wherein a first logic signal and a second logic signal are used as external control signals, and wherein the first logic signal and the second logic signal are used. Logic state detection means for detecting a logic state of the second logic signal when the first logic signal changes to a first logic state.
When the logic state is detected, the data of the memory cell is held in the output buffer. After that, the logic state detection means detects when the first logic signal changes to the second logic state. The semiconductor memory device outputs the data held in the output buffer to the outside when detecting that the second logic signal is in the second logic state. 2. The method according to claim 1, wherein said logic state detecting means detects that said second logic signal is in said first logic state when said first logic signal changes to said first logic state. ,
When the logic state detecting means detects that the second logic signal has changed to the second logic state after a lapse of a predetermined time, the logic state detection means externally stores the data in the output buffer. Then, the logic state detecting means determines that the second logic signal is in the first logic state when the first logic signal changes to the second logic state. 2. The semiconductor memory device according to claim 1, wherein when detected, the data held in the input buffer is written to a memory cell. 3. A semiconductor memory device employing an address multiplex system, wherein a first logic signal and a second logic signal are used as external control signals, and wherein said first logic signal and said second logic signal are used. Logic state detection means for detecting a logic state of the second logic signal when the first logic signal changes to a first logic state.
When the logic state is detected, the data of the memory cell is held in the output buffer. After that, the logic state detection means changes the second logic signal to the second logic state after a lapse of a predetermined time. A semiconductor memory device, wherein refreshing of a memory cell is performed when it is detected that no operation is performed. 4. A semiconductor memory device employing an address multiplex system, wherein a first logic signal and a second logic signal are used as external control signals, and wherein said first logic signal and said second logic signal are used. Logic state detection means for detecting a logic state of the second logic signal when the first logic signal changes to a first logic state.
When the logic state is detected, the data of the memory cell is held in the output buffer. After that, the logic state detection means changes the second logic signal to the second logic state after a lapse of a predetermined time. When it is detected that the first logical signal has changed, when the first logical signal changes to the second logical state, the logical state detecting means changes the second logical state. When detecting that the logic signal is in the second logic state,
A semiconductor memory device comprising: writing data held in the input buffer to a memory cell after outputting data held in the output buffer to the outside; 5. When the logic state detecting means detects that the second logic signal is in the second logic state when the first logic signal changes the first logic state. ,
5. The semiconductor memory device according to claim 1, wherein a row is selected by an internal circuit.