JPH03152789A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the reduction of the number of external control signals and timing requirement between the external control signals by using first and second logic signals as the external control signals, and performing the first and second logic state change of the first logic signal within one cycle sequentially. CONSTITUTION:For example, in the case of executing a normal read mode, data in a memory cell 20 is transmitted to and is held with an output buffer 29 when the fist logic signal S1 performs the first logic state change 'L' 'H' and it is detected that the second logic signal S2 is set at the logic state 'H' on one side, and after that, when the first logic signal S1 performs the second logic state change 'H' 'L' and it is detected that the second logic signal S2 is set at the logic stage 'L' on the other side, the data held in the output buffer 29 is outputted to the outside. In such the way, the number of external control signals can be reduced in the semiconductor memory device employing an address multiplex system such as a DRAM and the reduction of the timing requirement between the external control signals can be attained.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Fig. 4, Fig. 5 A-F) Problems to be solved by the invention Examples of means and actions for solving the problems (Fig. 5 A-F) 1, FIGS. 2A-G, and FIG. 3) Structure of one embodiment Operation of one embodiment Effects of one embodiment Effects of the invention [Summary] Semiconductor memory device adopting address multiplex method for address input method , for example, dynamic R
Regarding AM, the RAS signal and CA
The S signal is aggregated into one phase signal, and the WE signal and OE signal are aggregated into another one phase signal, so that the conventional operation mode can be executed.

[Industrial Application Field] The present invention relates to an address input method, and an address multiplex method (address multiplex method).
The present invention relates to a semiconductor memory device employing g), for example, a dynamic RAM (hereinafter referred to as DRAM).

In such a semiconductor memory device, RAS (row address 5 trobe) is used as an external control signal.
Signal, CAS (colua+n address
5trobe) signal, WE (write enable)
) signal and an OE (output enable) signal are required.

[Prior Art] Conventionally, semiconductor memory devices, such as DRAMs, employ an address multiplex method for address input.
As shown in Fig. 4, a system has been proposed.

In the figure, 1 is a memory cell array, 2 is a row address buffer, 3 is a row decoder, 4 is an address counter, 5 is a column address buffer, 6 is a column decoder, and 7 is an I1
0 gate, 8 is sense amplifier, 9 is input buffer, 10
is the output buffer.

Further, 11 is a first clock generator, and this first clock generator 11 receives the RAS signal and outputs the first clock signal.

Note that this first clock signal is applied to the row address buffer 2, row decoder 3, sense amplifier 8, and output buffer 1.
0 and is supplied to a write clock generator 17, which will be described later.

Further, 12 is a delay circuit, 13 is a second clock generator, and 14 is an ATD (address transistor).
-ion detector) activation signal generation circuit;
15 is the ATD circuit, 16 is CLS (column
1ine 5elect) Gate control signal-B L L
(bus 1ine 1atch) signal generation circuit, 1
7 is a light clock generator.

The delay circuit 12 delays the first clock signal generated by the first clock generator 11 and supplies it to the second clock generator 13. Also, the second
The clock generator 13 outputs a second clock signal and supplies this to the column address buffer 5, the ATD activation signal generation circuit 14, and the write clock generator 17.

Further, the ATD activation signal generation circuit 14 outputs an ATD activation signal and supplies it to the ATD circuit 15 to activate the ATD circuit 15.
outputs the ATD signal, which is used as the CLS gate control signal/
It is supplied to the BLL signal generation circuit 16.

In addition, the CLS gate control signal/BLL signal generation circuit 16
outputs a CLS gate control signal and a BLL signal, of which the CLS gate control signal is supplied to the column decoder 6, which generates the CLS signal, and the BLL signal is supplied to the output buffer 10. , the data appearing on the bus line is latched into the output buffer 10.

In addition, the write clock generator 17 receives the first clock signal, the second clock signal, the CAS signal, and the WE signal, outputs a write clock signal, supplies this to the input buffer 9, and outputs the write clock signal from the outside. This allows the input buffer 9 to latch data.

Reference numeral 18 denotes a CBR (CAS before RAS) signal generation circuit, which receives the RAS signal and the CAS signal and outputs a CBR signal, which is sent to the ATD activation signal generation circuit 14, the row address buffer 2, the address This is supplied to the counter 4. This CBR signal is
Used when executing AS-before-RAS-refresh mode.

In such a conventional DRAM, the operation mode is as follows.
As shown in the respective time charts in FIG. 5C, ■Normal read mode (also simply called read mode, a mode in which data is read from memory cells; see FIG. 5C); ■Normal/Light/
mode (also simply called write mode, a mode in which data is written to memory cells.

(See Figure 5 C), ■RAS・Only Refresh・
mode (a mode in which refresh is performed by only reading and rewriting specified rows).

(See Figure 5C), ■ Read-modify-write mode (also called read-write mode, which has normal read mode and normal write mode).
A mode that combines modes.

(see Figure 5), ■CAS-before-RAS-refresh mode (a refresh mode in which a refresh address is internally generated using address counter 4; see Figure 5C), ■Hidden refresh mode
mode (a mode in which data output in read mode is held in the output buffer 10 and CAS, before, RAS, and refresh modes are executed in the next cycle).

Six modes (see FIG. 5C) can be executed.

[Problems to be Solved by the Invention] However, in the conventional DRAM shown in FIG. 4, in order to execute the various modes described above, the RAS signal,
Four external control signals are required: a CAS signal, a WE signal, and an OE flaw signal, and necessary timing must be set between these four external control signals. Therefore, there is a problem in that a considerable amount of timing regulations are required just for writing and reading.

In view of the above, an object of the present invention is to reduce the number of external control signals and reduce the timing regulations between external control signals in a semiconductor memory device such as a DRAM that employs an address multiplex method.

[Means for Solving the Problems] In the semiconductor memory device of the present invention, first and second logic signals are used as external control signals.

Regarding the first logic signal, a first logic state change (for example, a logic state change from "L" to "H", the same applies hereinafter) and a second logic state change (for example, a logic state change from "L" to "H") and a second logic state change (for example, Logic state change from H'' to L'°.The same applies hereafter.)
(Example drawings Fig. 2 A to G)
, see 81 and S2 in FIG. 3).

Further, logic state detection means for detecting the logic states of the first and second logic signals is provided inside the chip, and the chip is configured to perform the following operations.

(1) When the first logic signal changes the first logic state, the second logic signal changes to one logic state (for example, °°H°“
. Same below. ), the data in the memory cell is transmitted to the output buffer and held there, and then, when the first logic signal undergoes a second logic state change, the second logic signal is If the signal is in the other logic state (e.g. L゛°
. (same below), the data held in the output buffer is output to the outside (see FIG. 2A).

(2) On the other hand, when it is detected that the second logic signal has changed to the other logic state after a predetermined time has elapsed after the first logic signal has undergone the first logic state change, the input After data is loaded into the buffer, when the first logic signal changes the second logic state and it is detected that the second logic signal is in one of the logic states, the data is input to the input buffer. Write the retained data to the memory cell (
(See Figure 2B).

When configuring to perform the above operations, ■Normal read mode, ■Normal write mode
mode, ■ST-only refresh mode (corresponding to the conventional RAS-only refresh mode).
(See Figures A-C).

Note that after a predetermined time has elapsed since the first logic signal changed the first logic state, the second logic signal changes to the other logic state, and then the logic state of the second logic signal changes. does not change, the first logic signal makes the first logic state change, and when the second logic signal is detected to be in the other logic state, the data held in the output buffer is If the configuration is such that the data held in the input buffer can be written to the memory cell after reading, in addition to the modes ■ to ■ above, in addition to ■ read-modify-write mode. can be executed (see second diagram).

Further, when the first logic signal changes the first logic state and it is detected that the second logic signal is in the other logic state, the row address is selected by the internal circuit. Can be configured. In this case, the above
In addition to ■, it is also possible to execute ■S2-before-STrefresh mode (corresponding to the conventional CAS-before-RAS-refresh mode) and ■hidden refresh mode (second Figure F,
(see G).

[Operation] In the present invention, the above mode can be implemented by setting the timing relationship of the second logic signal to the first logic signal as follows.

(1) Normal read mode (see Figure 2A) When this mode is executed, when the first logic signal changes the first logic state, the second logic signal changes to one logic state. , and after a predetermined period of time has passed and before the first logic signal changes the second logic state, the second logic signal is set to the other logic state, so that the first logic signal changes. When performing the second logic state change, the second logic signal is caused to be in the other logic state.

In this way, when the first logic signal undergoes the first logic state change, it is detected that the second logic signal is in one logic state, so that the data in the memory cell is transmitted to the output buffer. and retained. Thereafter, when a predetermined period of time has elapsed, the second logic signal does not become the other logic state, but becomes the other logic state after the predetermined period of time has elapsed. Therefore, no write operation is performed.

Then, in this example, when the first logic signal subsequently undergoes a second logic state change, the second logic signal is detected to be in the other logic state, so the second logic signal is held in the output buffer. The collected data is output to the outside.

In this way, normal read mode is executed.

(2) Normal write mode (see Figure 2C) When this mode is executed, when the first logic signal changes the first logic state, the second logic signal changes to one logic state. Then, when the predetermined time has elapsed, the second
set the logic signal of the other logic state, and then
The second logic signal is returned to one logic state before the logic signal makes the second logic state change.

In this way, when the first logic signal undergoes the first logic state change, it is detected that the second logic signal is in one logic state, so that the data in the memory cell is transmitted to the output buffer. When the second logic signal is set and held or a predetermined time period elapses, the second logic signal becomes the other logic state and this is detected, so that data supplied from the outside is taken into the input buffer. Then, when the first logic signal changes the second logic state, it is detected that the second logic signal is in one logic state, so the data taken into the input buffer is transferred to the memory cell. will be written to.

In this way, normal write mode is executed.

(3) Sl-only refresh mode (see Figure 2C) When executing this mode, the first logic signal is
and maintaining the second logic signal at one logic state while performing the second logic state change.

In this way, when the first logic signal undergoes the first logic state change, it is detected that the second logic signal is in one logic state, so that the data in the memory cell is transmitted to the output buffer. and retained. Thereafter, when a predetermined period of time has elapsed, the second logic signal does not change to the other logic state, so data from the outside is not taken into the power buffer, and the first logic signal changes to the second logic state. When the state is changed, it is detected that the second logic signal is in one of the logic states, so that the data held in the output buffer is not output to the outside. however,
Since the data has been transferred to the output buffer, the memory cells are refreshed.

In this way, the ST-only refresh mode is implemented.

(4) Read-modify-write mode (see second diagram) When executing this mode, the first logic signal
When performing a logic state change, the second logic signal is set to one logic state, and then, when a predetermined period of time has elapsed,
The second logic signal is put into and then maintained at the other logic state so that it is in the other logic state when the first logic signal makes a second logic state change.

In this way, when the first logic signal undergoes the first logic state change, it is detected that the second logic signal is in one logic state, so that the data in the memory cell is transmitted to the output buffer. and retained. Further, when a predetermined period of time has elapsed, the second logic signal becomes the other logic state, and this is detected, so that data supplied from the outside is taken into the high-power buffer. Thereafter, when the first logic signal undergoes a second logic state change, it is detected that the second logic signal is in the other logic state, so the data taken into the output buffer is transferred to the memory cell. written.

In this way, the read-modify-write mode is executed.

(5) S2-before-STrefresh mode (see Figure 2C) When executing this mode, the first logic signal is
When performing a logic state change, the second logic signal is at the other logic state.

In this way, when the first logic signal makes the first logic state change, it is detected that the second logic signal is in the other logic state, so that the row address is selected by the internal circuit. . At this point, an S2-before-S-refresh mode can be executed.

[Embodiment] Hereinafter, an embodiment of the present invention will be explained in terms of configuration, operation, and effects with reference to FIGS. 1 to 3. Note that this embodiment is a case where the present invention is applied to a DRAM.

(6) Hidden refresh mode (see Figure 2 F, G) ■ Set the next cycle of read mode to 82.before.S.
It can be set to refresh mode, so
By doing this, hidden refresh
mode (see Figure 2F).

■The cycle following the read/write mode can be set to the 82-before-S refresh mode, so by doing so, the hidden refresh mode can be executed (see Figure 2). (see G).

1) FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, and FIGS. 2A to 2G are time charts showing various operation modes of the embodiment of the present invention. In the example, the first and second logic signals, which are external control signals, are shown in FIG.
Logic signals S1 and S2 as shown in G (hereinafter simply referred to as SL)
, S2) are used.

Here, in FIG. 1, 20 is a memory cell array;
1 is a row address buffer, 22 is a row decoder, 23
is an address counter, 24 is a column address buffer,
25 is a column decoder, 26 is an I10 gate, and 27 is a sense amplifier, which are constructed in the same manner as the conventional example shown in FIG.

Further, 28 is an input buffer, 29 is an output buffer, and the input buffer 28 is a WAE (write) buffer, which will be described later.
data supplied from the outside is latched by the am+p enable) signal, and the WDR (write dr
iver) signal so that a write operation can be performed. In addition, the output buffer 29
It is configured to be able to output data in response to a P E (ot+tput enable) signal.

Further, 30 is the first 81 delay circuit, 31 is the RLS (r
ow 1ine 5elect ) signal - CA E (
column address enable) signal/R
A L (row address latch > signal - S A L (5ense amp 1latch)
Signal generation circuit, 32 is RLS-CAE-RAL-S
This is an AL reset signal generation circuit.

Here, the first 81 delay circuit 30 delays Sl for a certain period of time and transmits it to the RLS signal, CAE signal, RAL signal, and S1.
It is supplied to the AL signal generation circuit 31. Also, R
The LS signal/CAE signal/RAL signal/SAL signal generation circuit 31 responds to the delayed Sl to generate signals E, D,
It outputs RLS signals, CAE signals, RAL signals, and SAL signals as shown in C and F. Also, RLS・
The CAE-RAL-SAL reset signal generation circuit 32 outputs RLS-CAE/RAL-SAL to the RLS signal/CAE signal-RAL signal/SAL signal generation circuit 31.
Provides reset signal, RLS signal, CAE signal, RA
This resets the L signal and SAL signal.

Note that the RLS signal is supplied to the row decoder 22 to activate it and select a word line. Further, the CAE signal is supplied to the column address buffer 24 to control reception of column addresses. Further, the RAL signal is supplied to the row address buffer 21, and the column address buffer 21 responds to the CAE signal.
The row address buffer 21 is latched so as to inhibit the input of a row address to the row address buffer 21 in response to the column address reception enabled state of the row address buffer 21. Further, the SAL signal is a signal obtained by delaying the RLS signal, and is supplied to the sense amplifier 26 to drive the sense amplifier 26, and is also supplied to the ATD activation signal generation circuit 33 to drive it and activate the ATD. It generates a signal.

Further, numeral 34 is an ATD circuit, and numeral 35 is a CLS gate control signal/BLL signal generation circuit, which are constructed in the same manner as the conventional example shown in FIG.

Further, 36 is an OPE signal generation circuit, and 37 is an OPE signal delay circuit.The OPE signal generation circuit 36 receives supplies of Sl and S2, outputs an OPE signal, and transfers this OPE signal to an output buffer 29 and an OPE signal. This signal is supplied to the delay circuit 37.

Further, the OPE signal delay circuit 37 delays the OPE signal.

Further, 38 is a WAE signal generation circuit, 39 is a WDR signal generation circuit, and 40 is a WAE reset signal generation circuit,
The WAE signal generation circuit 38 generates the first 81 delayed signal and S2
The WAE signal is output from the WAE signal. Further, the WDR signal generation circuit 39 receives the WAE signal and the OPE delay signal, outputs a WDR signal, and supplies this to the input buffer 28. Further, the WAE reset signal generation circuit 40 receives the WAE signal and the WDR signal, outputs a WAE reset signal, and supplies this to the WAE signal generation circuit 38.

Note that 41 is S 2 B S 1 (S2 before
e Sl) signal generation circuit, S2, before, S
This circuit is used when executing the refresh mode, and generates a 32BS1 signal as shown in FIG. 3P.

42 also performs RLS when executing normal read mode, ST-only refresh mode, etc.
-CAE -RAL-SAL reset signal generation circuit 32
This is a circuit for instructing the timing of reset to the 81-bit circuit, and is configured by providing a second 81 delay circuit 43, an inverter 44, and a NOR circuit 45.

- (Refer to Figures 2 and 3) Normal read mode (Refer to Figures 2A and 3) (1) When Sl becomes "H" (Figure 3A) After a delay of a predetermined time, the ■RLS signal is generated and the word line selection operation is started (Fig. 3E), the ■CAE signal is generated, and the column address can be accepted (Fig. 3D). ), also R
An AL signal is generated and latched so that input to the row address buffer 21 is prohibited (FIG. 3C),
Also, the SAL signal is generated, the sense amplifier 27 is driven, and the data of the memory cells spilled into each column is amplified (FIG. 3F).

(2) As the SAL signal is generated, the ATD activation signal generation circuit 33 is driven and the ATD circuit 34 is activated (FIG. 3H). ■The CLS signal is generated by the column decoder 25 (Fig. 3 I), and ■The data appearing on the bus line is latched into the output buffer 29 by the BLL signal (
Figure 3 J, 0).

(3) After that, when Sl changes to “L”, S2 changes to °“
When it is detected that the output voltage is "L", the data latched in the output buffer 29 is outputted by the generation of the OPE signal (M in FIG. 3).

(4) When SL becomes “L” and this is delayed for a certain period of time by the second 81 delay circuit 43, the NOR circuit 45
The output becomes “H” and RLS - CAE - RAL
-SAL reset signal generation circuit 32 is activated and C
The AE signal and RLS signal are reset (3rd diagram, E).

(5) By resetting the CAE signal, ■RAL signal is released (Fig. 3C), and by resetting the RLS signal, ■SAL signal is released (Fig. 3F), and ■ATD activation signal generation circuit 33 The ATD circuit 34 is reset and the ATD circuit 34 is inactivated (H in FIG. 3).
4 is deactivated, ■CLS signal reset (third
(2) in Figure 3) and the BLL signal is released (J in Figure 3).

The normal read mode is executed in the above manner.

■, normal write mode (see Figures 2B and 3) (1) The first 81 delay circuit 30 is executed in parallel with (1)-■ to ■ of the normal read mode. When the output signal 82 changes to "Lo" at the time when the output signal becomes "L" (broken line in FIG. 3), the WAE signal is generated, the input buffer 28 is activated, and the data supplied from the outside is output. is latched (L in Figure 3).

(2) After (2) -■ to ■ in the normal read mode are performed, when ■S1 changes to L'° and it is detected that S2 is ゛H, the WDR signal is Occurrence number 3
(Fig. N), (2) According to the data taken into the input buffer 29, the bus line is forcibly set, and data is written by transmitting the data to a predetermined column.

(3) After the WDR signal rises, the WAE signal generation circuit 3 is activated by the operation of the WAE reset signal generation circuit 40.
8 is reset (L in Figure 3), and as part of this process, the WDR signal generation circuit 39 is also reset (N in Figure 3).
).

(4) By resetting the WDR signal, steps (4) and (5)-■ to ■ of the normal read mode are executed.

The normal write mode is executed in the above manner.

1[,s-only refresh mode (Figure 2C
1Refer to Figure 3. (1) This is an operation to rewrite the memory cell using (1) -■ to ■ of the normal read mode, but normally, (2) of the normal read mode is used. - The circuit operations from ■ to ■ are performed.

(2) The CAE signal and RLS signal are reset in a state where Sl is "L" and S2 is "H'" and the WAE signal is not generated.

(3) After that, normal read mode (5) -■
～■ will be carried out.

In the above manner, the ST-only refresh mode is executed.

■, Read-modify-write mode (Fig. 2D
, see Figure 3) (1) Normal read mode and normal write mode
In a mode in which the modes are combined, (1)-■ to ■ of the normal write mode are performed first.

(2) After that, normal read mode (2)-■
~■ and (3) are performed.

(3) Then, after the OPE signal delay circuit 37 has elapsed after the OPE signal is generated, the WDR signal generation circuit 39 is driven, and the normal write mode is set to (2) -■ to ■, <3)
-■ to ■, (4) are subsequently performed.

The read-modify-write mode is executed as described above.

V, S2 Before S refresh mode (second
(See Figure E and Figure 3) (1) When Sl becomes "H" and S2 is "L", ■92BS1 signal generation circuit 41 is driven (see Figure 3, P
), (2) The address signal from the address counter 23 is switched so that it is input to the row address buffer 21.

(2) After that, based on the address signal input to the row address buffer 21, the ST-only refresh
Rewriting to the memory cell is performed in the same manner as in the mode.

In the manner described above, the S2-before-STrefresh mode is executed.

(2) Hidden refresh mode (see FIGS. 2F and G, and FIG. 3) This mode can be performed by the following two types of operations.

■-1. The data output in the normal read mode is held by setting S2 to “L”, and in the next cycle, the S2-before-S-trifresh mode is executed (the Figure 2 F).

■-2. Data output in read-modify-write mode is held by setting 82 to "L", and S2-before-S-trifresh mode is executed in the next cycle. (Figure 2G).

Varnish 1j Reli 11 As described above, according to this embodiment, as in the case of the conventional example shown in FIG.
Write mode, ■S-only refresh mode, ■Read-modify-write mode, ■S2
It is possible to execute six modes: ・Before S refresh mode and ■Hidden refresh mode, but the external control signals required are two logic signals S
1 and S2 are sufficient, and as in the conventional example in Fig. 4, the RAS signal,
There is no need for four external control signals: CAS signal, WE signal, and OE signal. Therefore, it is possible to reduce the timing regulations for external control signals.

In addition, in the present invention, as long as the logical states of Sl and S2 have the timing shown in FIG. 2, (1) If S1 is as shown in FIG. ■S
1 is the opposite of the case shown in FIG. 2, and S2 is as shown in FIG. It can be configured to obtain the following effects.

Further, in the above embodiments, the case where the present invention is applied to a DRAM has been described, but the present invention is also applicable to semiconductor memory devices that adopt an address multiplex method, for example,
It can also be applied to SRAM.

[Effect of the invention] According to the present invention, the following effects can be obtained.

That is, according to the invention set forth in claim 1, ■normal read mode, ■normal write mode, and ■ST-only refresh mode can be executed, and according to the invention set forth in claim 2, In addition to the above modes ■ to ■, it is also possible to execute a read-modify-write mode, and according to the invention described in claim 3, the above-mentioned
In addition to the modes ~■, it is also possible to execute ■S2-before-STrefresh mode and ■hidden refresh mode, but in either case, two external control signals are sufficient, so four external control signals are required. Compared to conventional semiconductor memory devices that require several external control signals, the timing regulations between external control signals can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing essential parts of an embodiment (DRAM) of the present invention, FIGS. 2A to 2G are time charts showing operation modes of an embodiment of the present invention, and FIG. Time chart showing normal read mode, Figure 2B is a time chart showing normal write mode, Figure 2C is a time chart showing S-only refresh mode, Figure 2 is read-modify-write.・Time chart showing the modes; Figure 2 E is a time chart showing S2-before-S refresh mode; Figure 2 F is a time chart showing an example of hidden refresh mode; Figure 2 G is a time chart showing an example of hidden refresh mode. 3 is a time chart showing various internal signals of an embodiment of the present invention; FIG. 4 is a block diagram showing main parts of an example of a conventional DRAM; Figures A to F are time charts showing the operation modes of the conventional example shown in Figure 4. Figure 5 A is a time chart showing the normal read mode, and Figure 5 B is a time chart showing the normal write mode. , Figure 5C is a time chart showing RAS-only refresh mode, Figure 5 is a time chart showing read-modify-write mode, Figure 5E is CAS-before-RAS-refresh mode.
Figure 5F is a time chart showing the hidden refresh mode. Sl: First logic signal S2: Time chart showing second logic signal Sl - Time chart read mode showing normal in the embodiment Fig. 2A Time chart mode 1 showing normal read in conventional example Time chart showing the S-only refresh mode in one embodiment FIG. 2C Time chart showing the RAS-only refresh mode in the conventional example FIG. 5 Time chart showing C 1 Time chart FIG. Time chart 1 showing the write mode 2nd time chart showing the read-modify-write mode in one embodiment Time chart 5 showing the read-modify-write mode in the conventional example D 52 in one embodiment Time chart showing and forward refresh mode FIG. 5 E - Time chart showing an example of front refresh mode in the embodiment FIG. 2 F Time chart showing front refresh mode in conventional example Time chart showing

Claims (3)

[Claims] (1) First and second logic signals are used as external control signals, and the first and second logic states of the first logic signal are sequentially changed within one cycle. and a logic state detection means for detecting a logic state between the first and second logic signals, and when the first logic signal changes the first logic state, the second logic signal changes. When one of the logic states is detected, the data in the memory cell is transmitted to the output buffer and held; thereafter, when the first logic signal changes the second logic state; , when detecting that the second logic signal is in the other logic state, outputs the data held in the output buffer to the outside; After the state change, when the predetermined time has elapsed and it is detected that the second logic signal has changed to the other logic state, data is taken into the input buffer, and then the second logic signal When the first logic signal changes the second logic state, when it is detected that the second logic signal is in one logic state, the data held in the input buffer is transferred to the memory cell. A semiconductor memory device characterized in that it is configured for writing. (2) When the predetermined time has elapsed after the first logic signal changes the first logic state, the second logic signal changes to the other logic state, and then the second logic signal changes to the other logic state. When the logic state of the logic signal does not change and the first logic signal changes the second logic state, when detecting that the second logic signal is in the other logic state, 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to write data held in the input buffer into a memory cell after reading data held in the output buffer. (3) When the first logic signal changes the first logic state and it is detected that the second logic signal is in the other logic state, the selection of the row address by the internal circuit 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to perform the following operations.