JPS5938997A - Storage device - Google Patents

Storage device

Info

Publication number
JPS5938997A
JPS5938997A JP14897682A JP14897682A JPS5938997A JP S5938997 A JPS5938997 A JP S5938997A JP 14897682 A JP14897682 A JP 14897682A JP 14897682 A JP14897682 A JP 14897682A JP S5938997 A JPS5938997 A JP S5938997A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
refresh
address
counter
refresh counter
selected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14897682A
Inventor
Tomoharu Nakamura
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Abstract

PURPOSE:To compensate the shift of content between an external refresh counter and a refresh counter in an IC, by outptting contents of the latter refresh counter when a refresh terminal is selected. CONSTITUTION:When a refresh control terminal REF is selected, the contents of the refresh counter 1 are incremented, and simultaneously, they are outputted from a refresh address output buffer 2 to an address buffer 3 and address input terminals A0-Ai. Address information given to the buffer 3 passes a decoder 4 to perform refreshing. Address information outputted to address input terminals is latched in an external refresh address counter, and it is used as the start address of refreshing when the control terminal REF becomes the non-selected state at the next time. Thus the shift of content between the external refresh counter and the refresh counter in the IC is compensated.
JP14897682A 1982-08-27 1982-08-27 Storage device Pending JPS5938997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14897682A JPS5938997A (en) 1982-08-27 1982-08-27 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14897682A JPS5938997A (en) 1982-08-27 1982-08-27 Storage device

Publications (1)

Publication Number Publication Date
JPS5938997A true true JPS5938997A (en) 1984-03-03

Family

ID=15464886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14897682A Pending JPS5938997A (en) 1982-08-27 1982-08-27 Storage device

Country Status (1)

Country Link
JP (1) JPS5938997A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617533A (en) * 1984-03-30 1986-01-14 Echiyuudo E Komerushiyarizashi Electric control type storage battery breaker
JPH02105389A (en) * 1988-10-13 1990-04-17 Matsushita Electron Corp Dynamic memory device
EP1751768A1 (en) * 2004-05-21 2007-02-14 Qualcomm, Incorporated Method and system for controlling refresh in volatile memories

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617533A (en) * 1984-03-30 1986-01-14 Echiyuudo E Komerushiyarizashi Electric control type storage battery breaker
JPH02105389A (en) * 1988-10-13 1990-04-17 Matsushita Electron Corp Dynamic memory device
JPH0434233B2 (en) * 1988-10-13 1992-06-05 Matsushita Electronics Corp
EP1751768A1 (en) * 2004-05-21 2007-02-14 Qualcomm, Incorporated Method and system for controlling refresh in volatile memories
EP1751768B1 (en) * 2004-05-21 2016-08-10 Qualcomm, Incorporated Method and system for controlling refresh in volatile memories

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