JPH02105389A - Dynamic memory device - Google Patents

Abstract

PURPOSE:To shorten the time required for the check to confirm a self-refresh operation by making use of the output of an address counter to measure the cycle of a refresh control signal produced internally. CONSTITUTION:The self-refresh operations are repeated with an internally produced refresh control signal 13 and an internal RAS signal 14 following the signal 13 after reception of a self-refresh operation command. The refresh addresses are counted up by an internal address counter circuit 7 every time the pulse of the signal 13 is produced. The output a0 - an of the circuit 7 are sent to an address buffer circuit 8 respectively and fetched there as the refresh addresses. Then it is required to know the time elapsed after reception of the self-refresh as well as the number of pulses of the refresh control signals produced in the period of said elapsed time to measure the cycle of the signal 13 at the self-refresh operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dynamic storage device having an asynchronous refresh operation function capable of retaining stored data with low power consumption.

2. Description of the Related Art In recent years, significant reductions in power consumption have been achieved in dynamic memory devices by adopting CMOS processes and devising circuits. As a result, the self-refresh operation has become important as a function that allows refresh operations to be easily performed with low power consumption by keeping the external refresh control input signal at a low level for a certain period of time. At times, batteries are used to hold stored information in small computers, and even in consumer devices that are powered by batteries.

A conventional dynamic storage device will be explained below. FIG. 3 is a block diagram of a control circuit for the self-refresh operation function of a conventional dynamic memory device, and FIG. 4 is a timing diagram of external input signals and internal control signals during the self-refresh operation. In Figures 3 and 4, 1 is a RAS (row address strobe) input signal, 2 is an RFSH (refresh) input signal, 3 is a control circuit for accepting self-refresh requests, and 4 creates a refresh control signal internally. 5 is a frequency dividing circuit for setting a cycle that satisfies refresh specifications; 6 is an internal refresh control signal generation circuit for generating an internal refresh control signal; 7
11 is the signal φO3C% at point P, 12 is the signal φQSCD at point Q, 113 is the signal REF I (internal refresh control signal) at point R, and 14 is the signal at 8 points. 1ntR
As (internal RAS), 17 is a power supply current waveform during self-refresh operation.

The operation of the dynamic storage device configured as described above will be described below.

As shown in FIG. 4, the RAS input signal 1 is kept at high level and the internal circuit is precharged for a time t.

Thereafter, the self-refresh control circuit 3 is activated by setting the RFSH input signal 2 to a low level, and a signal indicating the start of the self-refresh operation is generated. This signal starts the oscillation circuit 4, generates the basic clock φoscll for asynchronously generating an internal refresh control signal, and further divides the frequency using the frequency divider circuit 5 to meet the refresh specifications of the storage device. A signal φ03CD12 whose period is set to T is generated. The signal φoscD12 undergoes waveform shaping and pulse width optimization in the internal refresh control signal generation circuit 6, and becomes REFI (internal refresh control signal).
13, performs NAND logic with this and external RAS signal, and outputs the output as IntRAS (internal RAS signal) 1.
Set it to 4. The generation of the internal RAS signal performs a series of refresh operations, that is, latches and decodes the row address using the internal address counter, selects the word line, and then sets the word line level high to activate the switching transistor for memory cell access. After activating, reading out stored information to the bit line and amplifying it with a sense amplifier, the word line level can be set to a low level and operations can be performed up to rewriting the stored information.

With the above configuration, the self-refresh operation by the asynchronous internal RAS signal 14 is started after the RF SH input signal 2 becomes low level and time T/2 has elapsed.
After this, the refresh operation is repeated as long as the RFSH input signal 2 is kept at a low level and the RAS input signal 1 is kept at a high level. The self-refresh operation ends with RF S.
This is done by setting the H input signal 2 to a high level, and at this time the internal oscillation circuit 4 is stopped and the frequency dividing circuit 5 and internal address counter 7 are initialized.

Problems to be Solved by the Invention However, in the conventional configuration described above, in order to guarantee the self-refresh operation of the storage device during mass production, it is necessary to store information from outside the storage device that the internal refresh control signal REF113 is being generated at a cycle as designed. It is difficult to directly test using a functional testing device. For this reason, data is written to the storage device, and then a self-refresh operation is performed without performing a refresh operation until the time that the stored information can be retained is exceeded, and then the stored data is read out and checked to see if it matches the expected value. The test must be performed using a method, and it is not efficient as it takes time to test a storage device that has excellent retention characteristics of stored information. or,
The internal refresh control signal REF I 13 during self-refresh operation has a period of several tens of μ to reduce power consumption.
The power supply current waveform at this time has a peak of about 100 to 200 mA, matching the period of the internal refresh control signal REF113, and a width of several + nS, as shown in 17 in Fig. 4. have.

Therefore, there is a problem in that an expensive ammeter with a variable integration function is required to measure the power supply current during the self-refresh operation.

The present invention solves the above-mentioned problems, and provides a dynamic storage device that can efficiently perform inspection to confirm self-refresh operation function and measurement of power supply current during self-refresh operation in a short period of time. With the goal.

Means for Solving the Problems To achieve this object, the dynamic storage device of the present invention is configured to have a function of measuring the period of an internally generated refresh control signal using the output of an internal address counter. It is something.

Effect: With this configuration, after data is written to the storage device and a self-refresh operation is performed, the internally generated refresh control signal during self-refresh can be directly used without performing an inspection method that reads the stored data and confirms that it matches the expected value. Operation can be confirmed, reducing inspection time and increasing efficiency. In addition, if we can measure the period of the internally generated refresh control signal, we can measure the power supply current value during refresh operation using an external control signal with an operating period (several hundred nanoseconds) that can be measured with a normal ammeter that does not have an integral function. ,
It can be estimated by proportional calculation from the self-refresh operation cycle.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the control circuit for the self-refresh operation function of the dynamic storage device in this embodiment, and FIG. 2 shows the external input control signal and 5 shows a timing diagram of internal control signals. 9 is T E S T (test) input signal, 1.0 (
Ao=AN) is an external address input terminal, 15 (ao=a
o) is the output of the internal address counter circuit 7, and ao
is the least significant bit, ao is the least significant bit, 8 is an address buffer circuit, and 16 is a transfer gate. Note 1
．． 2.3.4, 5, 6.7, 11.12° and 13.14 are the same as those of the conventional example.

The operation of the dynamic storage device of this embodiment configured as described above will be described below. After accepting self-refresh operation, internally generated refresh control signal RE
F113 and the subsequent internal RAS signal 14 repeat the self-refresh operation. The refresh address is counted up by the internal address counter circuit 7 every time a pulse of the internally generated refresh control signal REF113 is generated, and the outputs aQ-ao of the internal address counter circuit 7 are respectively sent to the address buffer circuit 8 and taken in as a refresh address. . In order to measure the cycle of the internally generated refresh control signal REF113 during the self-refresh operation, it is sufficient to know the elapsed time after self-refresh reception and the number of pulses of the refresh control signal generated during that time. If the number of pulses is M, the output a of the internal address counter circuit 7 is
If Q -a is 1 when n is high level and 0 when it is low level, then M = 2n@ao+2n"a, -1+ -= +2・a
l+a.

becomes. Therefore, in this embodiment, the configuration is such that it is possible to output the output ao""an of the internal address counter circuit 7 to the outside of the storage device. That is, when the RFSH input signal 2 becomes low level and the TEST input signal 9 is made low level after time tD from the start of the self-refresh operation, the transfer gate 16 is turned on and the outputs ao to ao of the internal address counter circuit 7 are turned on. Each is output to external address input terminal 10 (Ao=AN). Therefore, by determining whether the output voltage level of each external address input terminal AC+-AN is high or low using a comparator (not shown) and performing the above calculation, the number of pulses of the internally generated refresh control signal REF I 13 generated during tD can be calculated. can be known, and the period can be determined by T=to/M.

Note that the TEST terminal is used to measure the period. Due to the terminal configuration of the package, this method can only be applied to storage devices that have an NC terminal, but there is no problem in terms of versatility if the measurement is performed on a wafer before sealing.

Effects of the Invention As described above, according to the present invention, it is possible to measure the period of an internally generated refresh control signal using the output of the internal address counter circuit, and this makes it possible to perform inspections to confirm self-refresh operation and self-refresh. A dynamic storage device that can efficiently measure the power supply current during operation in a short time can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a control circuit for the self-refresh operation function of a dynamic storage device according to an embodiment of the present invention, and FIG. 2 is an external input control circuit for measuring the period of an internally generated refresh control signal during self-refresh operation. Fig. 3 is a control circuit block diagram of the self-refresh operation function of a conventional dynamic storage device; Fig. 4 is a timing diagram of external input signals and internal control signals during the conventional self-refresh operation. It is a diagram. 1...RAS input signal, 2...RFS
H input signal, 3... Control circuit for accepting self-refresh request, 4... Oscillator circuit for basic clock generation to generate internal refresh control signal, 5
... Frequency divider circuit, 6 ... Internal refresh control signal generation control circuit, 7 ... Internal address counter circuit for refresh address generation, 8 ...
...Address buffer circuit, 9...TEST input signal, 10...External input terminal AO-AN, 1
1... Signal φosc at point P, 12...
...Signal φ0SCD% at Q point 13...
- Signal REFI at point R, 14... Signal rntRAs at 8 points, 15... Output aQ-an of internal address counter, 16... Transfer gate, 17... ...Current waveform during self-refresh operation.

Claims (1)

[Claims] In a dynamic storage device capable of self-refresh operation in which control signals necessary for refresh operation are internally generated and refresh is performed asynchronously with the outside, the cycle of the internally generated refresh control signal is determined by using the output of an internal address counter. What is claimed is: 1. A dynamic storage device characterized by having means for measuring.