JP2563715B2 - Dynamic storage - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic memory device having an asynchronous refresh operation function using a refresh address generated by an internal address counter.

[0002]

2. Description of the Related Art In recent years, various refresh operation functions have been installed as standard functions in dynamic memory devices.

That is, a function called RAS only refresh for performing a refresh operation by inputting a refresh row address and a control signal RAS (row address strobe signal) from the outside, and two kinds of control signals RAS and CAS (column address strobe) from the outside. Signal) and a refresh address is generated inside the memory device C
A function called AS before RAS auto-refresh, a function called 1-pin auto-refresh in which a control signal (RFSH) is input in a pulse form from the outside to generate a refresh address inside the storage device, and a control signal RFSH is externally set to a low level for a certain period By holding the memory device itself, there is a function called self-refresh in which the memory device internally generates the control signals and refresh addresses required for the refresh operation asynchronously. Above all, the self-refresh operation realizes low power consumption of the memory device. This is an important function that enables the stored information to be retained by the battery during a power failure.

FIG. 4 is a control circuit block diagram of a self-refresh operation function of a conventional dynamic memory device, and FIG.
FIG. 4 is a timing chart of external input signals and internal control signals during self refresh operation.

In FIGS. 4 and 5, 1 is a RAS (row address strobe) input signal, 2 is a CAS (column address strobe) input signal, 3 is a control circuit for accepting a self-refresh request, and 4 is an RAS signal internally. For generating a basic clock for generating a clock, 5 is a frequency dividing circuit for setting a cycle satisfying refresh specifications, and 7 is an internal RAS.
A control circuit for generating a signal, 9 is an internal address counter circuit for generating a refresh address, 10 is a signal φOSC 'at point F, 17 is a signal φOSCD' at point G, and 18 is H.
Signal RASI 'at the point 19 is the signal IntRA at the point I
S '.

As shown in FIG. 4, the self refresh control circuit 3 is activated by keeping the RAS input signal 1 at the high level and, after the precharge time tp of the internal circuit, bringing the RFSH input signal 10 to the low level. Then, a signal for informing the start of the self-refresh operation is generated. With this signal, the oscillation circuit 4 is started, and the basic clock φOSC'16 for asynchronously generating the internal RAS signal is generated,
Further, the frequency division circuit 5 is used for frequency division to generate a signal φOSCD′17 set to the cycle T ′ so as to satisfy the refresh specification of the memory device.

This signal φOSCD'17 is subjected to waveform shaping and pulse width optimization by the internal RAS generation control circuit 7, and then NAND logic of the signal RAS I'18 and the external RAS signal is taken and its output is the internal RAS signal. IntRAS'19. A series of refresh operations is performed by the generation of the internal RAS signal, that is, the row address is latched and decoded by the internal address counter, the word line is selected, and then the word line level is set to the high level to activate the memory cell access switching transistor. Then, after the stored information is read out to the bit line, amplified by the sense amplifier, the word line level is set to the low level, and the stored information can be rewritten.

With the above configuration, the self-refresh operation by the asynchronous internal RAS signal is started after the RFSH input signal becomes low level and T '/ 2 has passed,
After that, as long as the RFSH input signal is kept at the low level and the RAS input signal is kept at the high level, the refresh operation is repeated. The refresh operation is completed by setting the RFSH input signal to a high level, at which time the internal oscillator circuit is stopped and the frequency divider circuit is initialized.

[0009]

However, in the above-described conventional configuration, an RFSH input signal must be applied from the outside in order to perform the self-refresh operation, and an input terminal for that is required, which is a restriction on the terminal arrangement. .
In particular, if there is no NC (Non-Connection) terminal, that is, a vacant terminal, a terminal for RFSH input signal must be newly set. For this reason, the number of terminals increases, the package becomes large, and the mounting density decreases.

Further, it is necessary to generate the RFSH input signal as an independent signal externally, which requires a new external control circuit, which is not efficient.

An object of the present invention is to solve the above-mentioned problems, and an object thereof is to provide a dynamic memory device in which a self-refresh operation function can be mounted efficiently and with versatility.

[0012]

According to the present invention, a self-refresh control circuit for detecting a voltage change timing of a row address strobe signal and a column address strobe signal applied from the outside to accept a self-refresh request, and an output thereof. And circuit means for setting the memory device to the self-refresh operation state after being activated and a predetermined period has elapsed.

Further, according to the present invention, a refresh control circuit for activating an externally applied column address strobe signal prior to a row address strobe signal, detecting a timing at which the row address strobe signal is subsequently activated, and accepting a self refresh request. When the refresh operation period is controlled by an externally applied row address strobe signal, the memory device is self-refreshed after the predetermined period has elapsed. And circuit means for setting the operating state.

Further, according to the present invention, after detecting the timing of the voltage change of the row address strobe signal and the column address strobe signal applied from the outside, the row address strobe signal and the column address strobe signal are fixed to a constant voltage level for a certain period or more. By doing so, circuit means for performing a self-refresh operation is provided.

According to the present invention, the column address strobe signal applied from the outside is activated prior to the row address strobe signal, and after detecting the timing of activating the row address strobe signal, the row address strobe signal is kept for a certain period or more. By fixing the column address strobe signal to a low level, circuit means for performing a self-refresh operation is provided.

[0016]

According to the present invention, the storage device is set to the self-refresh operation state after a predetermined period has elapsed since the self-refresh request was accepted. Therefore, the refresh operation period can be controlled by the row address strobe signal applied from the outside within the predetermined period, and the storage device can be set to the self-refresh operation state after the predetermined period has elapsed.

Further, according to the present invention, after the self-refresh request is accepted, the self-refresh operation is performed by holding both the row address strobe signal and the column address strobe signal at a low level. If all are set to the ground level and only the power is supplied, the stored data can be retained.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a control circuit for a self-refresh operation function of a dynamic memory device according to the present embodiment, FIG. 2 is a timing chart of an external input control signal and an internal control signal during a self-refresh operation, and FIG. 3 is a self-refresh control circuit. It is an example of a logic circuit diagram.

RAS input signal 1 and CAS input signal 2
The self-refresh control circuit 3 having as input accepts the self-refresh request.

Self-refresh control circuit 3 includes inverters 31-34 and a NAND as shown in FIG.
It is composed of gates 35 to 37. In the standby state (standby state) shown at the left end of FIG. 2, the RAS signal 1 is at a high level and the CAS signal 2 is at a high level.
The output signal of the gate 37 is at high level. In this state, the oscillator circuit 4 in the subsequent stage is not activated.

From this state, the CAS signal 2 is first changed to a low level. At this timing, NA shown in FIG.
The output signal of the ND gate 37 remains high and does not change.

When the RAS signal 1 is changed to the low level after a predetermined delay time tD has passed after the CAS signal 2 has changed to the low level, the output signal of the NAND gate 37 shown in FIG. 3 changes to the low level. To do.

Such a self-refresh control circuit 3
The oscillation circuit 4 is activated by the change in the output signal of the above, a basic clock φOSC11 for generating the internal RAS signal is generated, and subsequently, the refresh cycle is set by the frequency dividing circuit 5,
After resetting and prohibiting acceptance of the RAS input signal by the external RAS control circuit 6, waveform shaping by the internal RAS generation circuit 7, and pulse width optimization, the NAND logic with the output of the external RAS input control circuit 6 is taken to determine the internal RAS. Signal I
ntRAS15.

Reference numeral 8 is an internal address counter control circuit for refresh address generation, 9 is an internal address counter circuit for refresh address generation, and 11 is a signal φOS at point A.
C and 12 are signals φOSCD at point B, and 13 is signal R at point C
ASO, 14 is a signal RASI at point D, and 15 is a signal IntRAS at point E.

Next, the operation of the dynamic memory device of this embodiment will be described. As shown in FIG.
The CAS input signal 2 is set to low level, and after the delay time tD,
By setting the RAS input signal 1 to a low level, the self-refresh control circuit 3 having the logic circuit configuration shown in FIG.
Receives the self-refresh request, activates the oscillation circuit 4 and internally generates the basic clock φOSC11 for asynchronously generating the RAS signal, and further performs frequency division by using the frequency division circuit 5 to refresh the memory device. A signal φOSCD12 whose period T is set to satisfy the condition is generated. This signal φOSCD12 is waveform-shaped by the control circuit 7 for generating internal RAS, and after the bit line potential is amplified and determined by the sense amplifier and reset, it is reset at a timing with a sufficient margin, and the pulse width is optimized to obtain the signal RAS14. Is the basis for generating.

On the other hand, after the self-refresh request is accepted by setting the phase and voltage conditions of the RAS and CAS input signals, the refresh operation can be repeatedly executed by holding the RAS and CAS input signals at the low level. Therefore, in the frequency dividing circuit 5, a signal having a cycle T / 2 one step before the final frequency dividing stage is obtained, and this is input to the external RAS input control circuit 6 as a reset signal,
The output signal RASO13 of the circuit 6 is reset and latched. As a result, after the CAS and subsequently the RAS signal become low level, the external RAS is
The internal RAS signal can be controlled by a signal, and thereafter, even if the external RAS signal is at a low level, internal reset is applied, and the internal RAS signal is controlled by an asynchronous signal generated by the self-refresh control circuit group.

The internal RAS signal IntRAS15 becomes a pulse signal having a cycle T as a NAND logic output of the signal RASI and the signal RASO, and holds the external CAS input signal at a low level to activate the internal address counter control circuit 8. It is possible to realize the self-refresh operation using the conventional auto-refresh function for generating the refresh address generated by using the internal address counter circuit 9.

The self-refresh operation is completed by
As is apparent from FIG. 3, this is performed by setting the input control signal of RAS1 or CAS2 to a high level, and at this time, the internal oscillator circuit is stopped and the frequency divider circuit is initialized.

[0029]

As described above, according to the present invention, by providing the control circuit group which enables the self-refresh operation by defining the phase timing and voltage of the row address strobe signal and the column address strobe signal. A dynamic memory device capable of mounting a self-refresh function efficiently and with versatility can be obtained without adding an input control signal terminal for self-refresh and an external control circuit.

Particularly in the present invention, after a predetermined period of time has passed since the self refresh request was accepted,
The storage device is set to the self refresh operation state. Therefore, the self-refresh function can be added without impairing the function such as the test cycle for checking the internal address counter.
Complete upward compatibility with the multi-address type dynamic memory device can be realized.

Further, according to the present invention, the auto-refresh or self-refresh mode can be determined by the length of the holding state of the row address strobe signal and the column address strobe signal applied from the outside.
It is easy to set timing from outside.

Further, according to the present invention, after the self-refresh request is accepted, the self-refresh operation is performed by holding both the row address strobe signal and the column address strobe signal at a low level. If all are set to the ground level and only the power is supplied, the stored data can be retained. Therefore, the power consumption of the self refresh operation can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a control circuit of a self-refresh operation function of a dynamic memory device according to an embodiment of the present invention.

FIG. 2 is a timing diagram of external input control signals and internal control signals during self refresh operation of the control circuit shown in FIG.

FIG. 3 is a logic circuit diagram showing an example of the self-refresh control circuit shown in FIG.

FIG. 4 is a block diagram of a control circuit of a self-refresh operation function of a conventional dynamic memory device.

FIG. 5 is a timing chart during a self refresh operation according to a conventional example.

[Explanation of symbols]

 1 RAS (row address strobe) input signal 2 CAS (column address strobe) input signal 3 self-refresh control circuit 4 oscillator circuit 5 frequency divider circuit 6 external RAS input control circuit 7 internal RAS generation control circuit 8 internal address counter control circuit 9 Internal address counter circuit 10 RFSH (refresh) input signal

Claims (1)

(57) [Claims] 1. A row address strobe externally applied.
Input signal by the column signal and the column address strobe signal.
Dynamics that control the read or write operation of the
In the memory device, the external row address strobe signal and the external column address signal are stored.
Refresh control circuit to which strobe signal is input
And the external row address strobe signal from the main operating circuit.
External row address strobe signal input control circuit
And a frequency divider circuit with multiple stages
Generates the set internal row address strobe signal
Local oscillator circuit and the internal address that generates the refresh address.
A dress counter circuit is provided , and in the refresh control circuit, the external column address is provided.
After the strobe signal goes low, the external line
When the dress strobe signal becomes low level
The refresh mode is accepted and the external column address is
Strobe signal and the external row address strobe
While the signal is kept low for a certain period of time,
The refresh mode is retained and the external column address scan
Strobe signal or external row address strobe signal
The refresh mode
-Has a control function to release the mode, and after the refresh mode is accepted, the plurality of
Reset signal from the predetermined frequency division stage in the frequency division circuit
To the external row address strobe signal input control circuit
At the input timing, the external line address
Signal is disconnected from the main operating circuit
While the mode is held, it is set by the internal oscillator circuit.
Internal row address strobe with fixed refresh cycle
Signal generated by the internal address counter circuit
The external row address based on the refresh address
Refresh operation is performed asynchronously with the strobe signal.
A dynamic storage device characterized in that