KR100557975B1 - Memory Auto Refresh Circuit_ - Google Patents

Abstract

The present invention relates to an automatic refresh circuit of a memory. Conventionally, in the distributed and burst automatic refresh methods, an automatic refresh command must be transmitted to a chipset at every operation, for example, 8k times during an 8k refresh operation. However, if the burst type is 16K refresh or more, there is a problem that the actual range of the lead / write can be narrowed. If the input command is automatically refreshed when the command set is input from the external system, the state determination unit 81 outputs an AREF signal, and the state determination unit 81 converts the internal refresh signal BAREF to an internal refresh signal when the AREF signal is input. An RS flip-flop 82 for outputting a driving signal BAi for driving a word line and a sense amplifier when the refresh signal is output from the oragate 91 and the oragate 91 A reference counter 83 that increases or decreases the address of the stored word line by inputting the refresh signal BAREF, and outputs a signal for indicating the address; and an address signal output from the reference counter 83 The DRAM core 84 performs a refresh operation by driving the word line and the sense amplifier of the address of the RS flip-flop 82 and the RS flip-flop 82. The refresh activation signal generator 86 generating and generating a refresh activation signal RE_RAS in which the refresh signal BAREF is synchronized with a clock and delayed by a desired time, and a count value when the refresh activation signal RE_RAS generated above is generated. Increases the value of 1 by 1 and the N_burst counter 85 outputs the refresh completion signal RE_BST, the inverter 88 inverts and outputs the signal output from the counter 85, and generates A delay 87 for delaying the refresh activation signal RE_RAS output from the unit 86 by tPUL time, an output signal of the refresh activation signal RE_RAS and the delay 87, and an output of the inverter 88; And gate (89) for signaling the signal and the time output unit 90 for delaying the signal output from the above by adjusting the tRP time to output to the other input terminal of the ora gate (91) For example, by automatically executing the desired number of refresh operations with one external system command and finishing, it eliminates the need to give a command each time and improves the system efficiency.

Description

Memory automatic refresh circuit

The present invention relates to an automatic refresh circuit of a memory that can perform a desired number of automatic refresh operations with one command, thereby eliminating the need to give a command each time. The present invention relates to an automatic refresh circuit of a memory to reduce power and improve system efficiency.

FIG. 4 is a block diagram of an automatic refresh circuit of a conventional memory. The AREF signal is determined by determining whether a command set such as RASB, CASB, CSB, CKE, etc. is an automatic refresh command from an external system. RS flip-flop (42) for outputting a state determining unit (41) for outputting a signal and a driving signal (BAi) for driving a word line and a sense amplifier stored when the AREF signal is output from the determining unit (41). And a reference counter 43 for increasing or decreasing one address of a word line stored when the AREF signal is input by the state determining unit 41 and outputting a signal AFXi indicating the address, and the reference counter. Comprising a DRAM core 44 for performing a refresh operation by driving the word line and the sense amplifier of the address for the address signal (AFXi) output from the (43) by the drive signal BAi of the RS flip-flop 42 do.

Looking at the prior art configured as described above is as follows.

First, when a command set such as RASB, CASB, CSB, CKE, etc. is input from an external system, the state determination unit 41 determines whether the command is automatic refresh.

As a result of the determination, if it is an automatic refresh command, the short pulse AREF signal is provided to the set input terminal S of the RS flip-flop 42 and to the reference counter 43.

When the AREF signal is input, the reference counter 43 increases or decreases the address of the currently stored word line by one, and the DRAM core 44 receives a signal AFXi corresponding to the address of the increased or decreased word line. )

At this time, when the RS flip-flop 42 is set by the AREF signal, the RS flip-flop 42 outputs a driving signal BAi for amplifying the word line and the sense amplifier in the DRAM core 44 to the DRAM core 44.

Therefore, the DRAM core 44 drives the word line and the sense amplifier of the address set by the reference counter 43 by the driving signal BAi to perform a refresh operation.

When the refresh is performed to some extent, it must be automatically reset to execute the next command, which causes the circuit designer to predict the time to be refreshed and give a delay so that the refresh end signal RE is generated after a certain time.

The refresh end signal RE thus produced is output from the DRAM core 44 and input to the reset input terminal R of the RS flip-flop 42.

The RS flip-flop 42 is then reset by the refresh end signal RE.

As the RS flip-flop 42 is reset, the driving signal BAi provided to the DRAM core 44 also becomes a reset state, thereby preventing the refresh operation.

In other words, the automatic refresh is executed in the system, and the reset command is executed after a set time after the set command.

As a result, the RS flip-flop 42 is composed of a noar gate NR1 NR2 and an inverter I as shown in FIG. 5, and the RS flip-flop 42 outputs the driving signal BAi in the set state. In order to output a high signal to the set input terminal S and a low signal to the reset input terminal R, the low signal is reset to the set input terminal S in order to output the driving signal BAi in the reset state. The high signal may be input to the input terminal R.

As described above, there are two methods for performing automatic refresh. In the first case, as shown in FIG. 1, the burst type automatic refresh giving 8k consecutive automatic refresh commands from the system to the memory during the tREF period is shown. In the burst auto refresh method, 8k refreshes are performed at a time to perform normal read / write commands for the remaining sections.

In the second case, as shown in FIG. 2, the most common method of periodically performing 8k commands in the system by performing a refresh at a specific section (tREF / 8k) is a distributed auto refresh method. to be.

1 and 2, the number and time when the memory controller issues a command based on the time of the refresh method based on the time tREF (maximum time that data can be held when the basic cell of the memory is not refreshed). Indicates.

Refresh is performed by activating a word line connected to the gate of a cell. When a chip having 8k wordline counts performs 8k refreshes (8 * 1024), it is called an 8k refresh product.

The cells on the first wordline that are performed first are returned to their turn after 8k times and receive a refresh command.

In the distributed automatic refresh method, the system cycle reference is shown in FIG. 3 to execute a single command. Referring to the system cycle reference, all active word lines must be reset in three cycles before executing the command (tRP). After that, no commands can come in until tRC has elapsed.

However, in the prior art as described above, in the case of the distributed and burst type automatic refresh method, the automatic refresh command must be transmitted to the chipset at every operation, for example, 8k times during the 8k refresh operation. In the case of more than 16K refresh, there is a problem in that the sequence as shown in FIG. 3 is performed every cycle, thereby narrowing the range for actually reading / writing.

Therefore, an object of the present invention for solving the conventional problems as described above is to automatically perform the desired number of refreshes in one external system command and then to finish the automatic refresh circuit of the memory to improve the system efficiency In providing.

Another object of the present invention is to provide an automatic refresh circuit of a memory to eliminate the trouble of having to give a command every time.

It is still another object of the present invention to provide an automatic refresh circuit of a memory that can be flexibly adjusted to a desired specification (tRC = tRAS + tRP).

The present invention for achieving the above object is a state determination unit for outputting the AREF signal when the input command is automatic refresh when the command set input from the external system, and by changing the internal refresh signal when the AREF signal input from the state determination unit An RS flip-flop that outputs a drive signal for driving a word line and a sense amplifier when the refresh signal is output from the refresh signal, and an address of the word line stored when the refresh signal is output from the oragate. A reference counter for increasing or decreasing one and outputting a signal for indicating the address, a word line of the address for the address signal output from the reference counter and a sense amplifier are driven by the drive signal of the RS flip-flop; DRAM core for performing a refresh operation and refresh output from the RS flip-flop A refresh activation signal generator for generating and generating a refresh activation signal delayed by a desired time by synchronizing the signal with a clock; and increasing the count value by 1 when the refresh activation signal is generated. An N_burst counter for outputting a signal, an inverter for inverting and outputting a signal output from the counter, a delay for delaying a refresh activation signal output from the generator by tPUL time, and a refresh activation signal and the delay of And an AND gate for ANDing the output signal and the output signal of the inverter, and a time adjusting unit for outputting the output signal to the other input terminal of the OA gate by adjusting the tRP time by delaying the output signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 8 is a block diagram of an automatic refresh circuit of a memory according to the present invention. As shown in FIG. 8, a state determination unit 81 outputs an AREF signal when an input command is automatically refreshed when an instruction set is input from an external system. The state determination unit 81 converts the internal refresh signal BAREF to an internal refresh signal BAREF when the AREF signal is input, and a driving signal for driving the word line and the sense amplifier when the refresh signal is output. Increasing or decreasing the address of the RS flip-flop 82 which outputs BAi and the word line stored at the time of input of the refresh signal BAREF output from the oragate 91 and informing the address thereof A reference counter 83 for outputting a signal for outputting the signal; and a word line and a sense amplifier of an address corresponding to the address signal output from the reference counter 83 to the driving signal of the RS flip-flop 82; By generating a refresh activation signal RE_RAS delayed by a desired time in synchronization with the clock and the refresh signal BAREF output from the RS flip-flop 82. The refresh activation signal generator 86 to increase the count value when the refresh activation signal RE_RAS is generated, and outputs the refresh completion signal RE_BST when the desired value is reached. ), An inverter 88 for inverting and outputting the signal output from the counter 85, a delayer 87 for delaying the refresh activation signal RE_RAS output from the generator 86 by tPUL time; And an AND gate 89 for ANDing the refresh activation signal RE_RAS, the output signal of the delayer 87, and the output signal of the inverter 88, and delaying the output signal from the output signal for a predetermined time. It is composed of a time adjusting unit 90 for adjusting the time and outputting to the other input terminal of the OA gate (91).

In addition, the refresh activation signal generator 86, as shown in Fig. 10, the RS flip-flop (F1) for outputting a signal delayed by a predetermined time when the BAREF signal is input to the set input terminal (S), and the RS flip N inverters (DF1-DF3) for sequentially outputting the time output from the flop F1 to be delayed by a desired time, and delaying the signals output from the flip-flop DF3 and then inverter I10 A first delay unit DLY1 for inverting and outputting the signal, and a NOR gate NR10 for generating a refresh activation signal RE_RAS by generating an output signal of the inverter I10 and the flip-flop DF3. do.

In addition, as shown in FIG. 12, the time adjusting unit 90 further includes an RS flip-flop F2, a deflip-flop DF3, and a second delay unit DLY2 which sequentially delay the input activation signal RE_RPS. And a noar gate configured to generate the pulse signal RE_RP for reactivation by generating an inverter I11 for inverting the output of the retarder and an output signal of the inverter I11 and the flip-flop DF3. NR11).

Referring to the operation and effect of the present invention configured as described in detail as follows.

When an external command set such as RASB, CASB, CSB, CKE, etc. is input from the external system, the state determination unit 81 determines whether or not the input command is an automatic refresh command.

As a result of determination, if the command is automatic refresh, the AREF signal, which is an internal command signal as shown in FIG. 9B, is output to the oragate 91 and the N_bust counter 85, respectively.

The AREF signal is then input to the N_burst counter 85 to initialize the count value.

The OR gate 91 generates a BAREF signal as shown in FIG. 9C and provides the BAREF signal to the set input terminal S and the reference counter 83 of the RS flip-flop 82.

Then, as the RS flip-flop 82 is set by the BAREF signal input to the set input terminal S, the driving signal BAi as shown in FIG. 9D is transferred to the DRAM core 84 to activate the word line and the sensor amplifier. At the same time, the reference counter 83 increases or decreases the address of the word line stored when the BAREF signal is input, and outputs a signal AFXi as shown in FIG. 9E to indicate the increased or decreased address. Output to the DRAM core 84.

Accordingly, the DRAM core 84 activates a word line by the signal BAi of the RS flip-flop 82 and the signal AFXi of the reference counter 83, and drives a sense amplifier to perform a refresh operation.

At this time, the refresh activation signal generator 86 receiving the BAREF signal output from the ora gate 91 is synchronized with the clock CLK, and the refresh activation signal RE_RAS is pulsed through the desired number of flip flops and delays. ) As in Figure 9f.

When the refresh activation signal RE_RAS generated by the refresh activation signal generator 86 is activated, this signal is input to the reset input terminal R of the RS flip-flop 82 to reset the RS flip-flop 82.

As the RS flip-flop 82 is reset, the BAi signal is inactivated and the refresh operation of the DRAM core 84 is completed.

When the refresh activation signal generator 86 shown in FIG. 10 provides the BAREF signal as shown in FIG. 11B to the set input terminal S of the RS flip-flop F1, the RS flip-flop F1 is The subsequent pulse is provided to the flip-flop (DF1-DF3).

Then, the flip-flops DF1 to DF3 are sequentially synchronized with the clock ACLK as shown in FIG. 11A to sequentially delay the input pulses by FIG. 11C to supply them to the first delay unit DLY1 and the NOA gate NR10, respectively. .

The signal input to the first delay unit DLY1 is delayed for a predetermined time and is supplied again to the other input terminal of the NOR gate NR10 through the inverter I10.

Then, the NOR gate NR10 generates and outputs the refresh activation signal RE_RAS as shown in FIG. 11D.

In addition, when the refresh activation signal RE_RAS of the refresh activation signal generator 86 is input to the N_burst counter 85, the N_burst counter 85 increments the count number once.

In addition, the refresh activation signal RE_RAS output from the refresh activation signal generator 86 and a delay signal of the delay unit DLY delaying the signal by tPUL time are input to the other input terminal of the AND gate 89. .

Therefore, the AND gate 89 NAND the signals input to the three input terminals, respectively, to generate the activation signal RE_RPS as shown in FIG. 9G, and output the generated signal to the time controller 90.

Then, the time adjusting unit 90 adjusts the tRP time by using a flip-flop and a delay, and outputs the adjusted pulse signal RE_RP to the other input side of the ora gate 91 as shown in FIG. 9H.

Accordingly, the OR gate 91 generates a BAREF signal by ORing the pulse signal RE_RP and the automatic refresh signal AREF output from the state determination unit 81 to generate the BAREF signal, thereby generating the RS flip-flop 82 and the reference counter ( 83) respectively.

The RS flip-flop 82 and the reference counter 83 then repeat the operation as described above.

When the activation signal RE_RPS as shown in FIG. 13B is input to the time adjuster 90 as shown in FIG. 12, the RS flip-flop F2 and the deflip-flop DF3 are clocked as shown in FIG. 13A. When a signal delayed by the same time as in FIG. 13C is provided in synchronization with the T1), the delay signal DLY2 and the inverter I11 generate and output the pulse signal RE_RP as shown in FIG. 13D.

In order to break this loop, the refresh execution completion signal RE_BST should be activated.

The refresh completion signal RE_BST is determined as the number of N_burst counters 85. For example, three refreshes are made if eight refreshes are desired, and thirteen counters are desired if 8k refreshes are desired.

Then, if eight refreshes are desired, when the eighth refresh activation signal RE_RAS is activated, the N_burst counter 85 outputs a high refresh completion signal RE_BST.

Then, the signal is inverted to the low state through the inverter 88 and input to the AND gate 89 to suppress the generation of the activation signal RE_RPS.

For this to be done, the tPUL time of delay 87 must be longer than the delay time of N_burst counter 85.

As explained so far, once an automatic refresh command is issued from an external system, the above operation is repeated.

In other words, as shown in FIG. 6, the remaining 8k-1 times can be operated internally with one command, and as shown in FIG. 7, seven internal operations are performed with one command and (tREF / 8k) * 8 again. Seven internal refresh operations can be performed with one command.

Therefore, the present invention has the effect of automatically completing the desired number of refresh operations with one external system command and then finishing the operation, thereby eliminating the trouble of having to give the command each time and improving the overall system efficiency.

1 is a timing diagram of a conventional burst type automatic refresh method.

2 is a timing diagram of a conventional distributed automatic refresh method.

3 is a system cycle waveform diagram for automatic refresh of a conventional pc 100 product.

4 is a block diagram of an automatic refresh circuit of a conventional memory.

5 is a detail and RS latch diagram of the RS flip-flop in FIG.

6 is a timing diagram of the present invention burst type automatic refresh method.

7 is a timing diagram of the present invention distributed automatic refresh method.

8 is a block diagram illustrating an automatic refresh circuit of the memory of the present invention.

9 is a signal timing diagram of each unit for performing FIG. 8;

FIG. 10 is a detailed view of a refresh activation signal generator in FIG. 8. FIG.

FIG. 11 is an input / output timing diagram of each unit for performing FIG. 10. FIG.

FIG. 12 is a detailed view of the time adjusting unit of FIG. 8. FIG.

FIG. 13 is an input / output timing diagram of each unit for performing FIG. 12. FIG.

*** Explanation of symbols for main parts of drawing ***

81: state determination unit 82: RS flip-flop

83: reference counter 84: DRAM core

85: N_ burst counter 86: refresh activation signal generator

87: delay unit 88: inverter

89: NAND gate 90: time control unit

91: Oagate

Claims (3)

If the input command is automatically refreshed when the command set is input from the external system, the state determination unit 81 outputs an AREF signal, and the state determination unit 81 converts the internal refresh signal BAREF to an internal refresh signal when the AREF signal is input. An RS flip-flop 82 for outputting a driving signal BAi for driving a word line and a sense amplifier when the refresh signal is output from the oragate 91 and the oragate 91 A reference counter 83 that increases or decreases the address of the stored word line by inputting the refresh signal BAREF, and outputs a signal for indicating the address; and an address signal output from the reference counter 83 The DRAM core 84 performs a refresh operation by driving the word line and the sense amplifier of the address of the RS flip-flop 82 and the RS flip-flop 82. The refresh activation signal generator 86 generating and generating a refresh activation signal RE_RAS in which the refresh signal BAREF is synchronized with a clock and delayed by a desired time, and a count value when the refresh activation signal RE_RAS generated above is generated. Is increased by 1, and when the desired value is reached, the N_burst counter 85 for outputting the refresh completion signal RE_BST, the inverter 88 for inverting and outputting the signal output from the counter 85, and the refresh A delay 87 for delaying the refresh activation signal RE_RAS output from the activation signal generator 86 for a predetermined time; an output signal of the refresh activation signal RE_RAS and the delay 87 and an inverter 88; And gate 89 for outputting the output signal of the time, and the time to output the output signal to the other input terminal of the ora gate 91 by adjusting the tRP time by delaying the signal output from the predetermined time Automatic refresh circuit of the memory, characterized in that consisting of hip (90). 2. The automatic refresh circuit of claim 1, wherein the refresh enable signal generator (86) generates a refresh enable signal (RE_RAS) using a flip-flop and a delay. 2. The automatic refresh circuit of claim 1, wherein the time adjuster (90) adjusts the tRP time using a flip-flop and a delay.