JP2001067878A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high-speed access in a memory circuit for writing and reading data in the asynchronous system. SOLUTION: The semiconductor storage is provided with a memory cell array MCA that is composed by an SRAM memory cell, means 117 and 118 for generating a pulse word signal PW by receiving an address change, an X-address register 111 and a Y-address register 112 for latching a write address, a data register 115 for latching write data, and a means 116 for latching each address and data at each register when writing the data and for generating a signal for outputting address and data being latched when writing data next. A word line WL of a memory cell array MCA is selected by an X address signal being outputted from the X address register 111 and the pulse word signal PW, a pair of digit lines D and /D of the memory cell array MCA is selected by a Y-address signal being outputted from the Y-address register 112, and data being outputted from the data register 115 is written into a memory cell that is selected by the selected word line and the pair of digit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM (Static Random Access Memory) circuit and a DRAM.
The present invention relates to a semiconductor memory device having a memory circuit such as a (dynamic random access memory) circuit, and more particularly to a semiconductor memory device having an increased access speed.

[0002]

2. Description of the Related Art Among recent memory circuits, an SRAM circuit has six transistors as shown in FIG.
A pair of NMOS-type driver transistors Tr1 and Tr2 whose gates and drains are cross-connected, and a gate is a word line W
L for connecting and disconnecting the driver transistors Tr1 and Tr2 to the digit line pair D and / D.
MOS access transistors Tr3, 4, driver transistors Tr1, Tr2 and access transistor T
A pair of PMOS type load transistors Tr5, 6 whose sources and drains are connected between the nodes N2, which are the connection points of r3, 4 and the circuit power source and whose gates are connected to the nodes N2, 1 are formed. , So-called 6Tr memory cells are mainstream. The load transistors Tr5, Tr5
Although there is also a configuration in which 6 is constituted by a load resistor, here, this configuration is also referred to as a 6Tr memory cell.

As a method of selecting a memory cell and writing / reading data to / from the SRAM cell having such a memory cell, there is an asynchronous method which does not use an external synchronization signal. In the asynchronous system, for example, as shown in FIG. 10, the write operation timing is changed after the address Add changes to / CS (chip select).
The signal / WE (write enable) signal is set to L (low level), and the memory cell is selected by selecting the word line WL and the digit line pair D and / D. Then, the data input to Din (data bus input) is written to the memory cell when the selected word is raised. However, in this asynchronous system, since it is necessary that the memory cell is selected while WE is at L, a through current flows from the circuit power supply to the memory cell through the digit line during that time,
There is a problem that current consumption increases. Further, if an address change occurs during the write operation, another address is selected and erroneous writing may be performed. Therefore, the time from when the / WE switches from L to H to the time when the address change is performed is performed. Time TWR must be secured.

On the other hand, an asynchronous method is used in which an external synchronous signal is not used, and an internal synchronous method in which a memory cell is selected based on a timing signal generated in a circuit and writing and reading are performed has been proposed. ing. In this internal synchronization system, a pulse word system in which current consumption is reduced by selecting a memory cell at the timing of writing and reading data is mainly used. In the pulse word method, as shown in the operation timing of FIG. 11, at the time of reading, a PW (pulse word) signal is generated in response to an address change and / CS = L, and a memory cell is selected by the PW signal. Perform a read operation.
At the time of writing, an address change, / WE = L, and a change in write data (data change) cause
A signal is generated, a memory cell is selected by the PW signal, and a write operation is performed. In the pulse word method, memory cells are selected only at the timing of a read operation and a write operation. Therefore, compared to the above-mentioned conventional asynchronous method, the time during which a memory cell is selected can be reduced, and current consumption can be reduced. It is effective in reducing.
An SRAM circuit employing this kind of pulse word system is disclosed in Japanese Patent Application Laid-Open No. 5-74162.

[0005]

In the pulse word method, if a data change occurs a plurality of times during a long cycle write operation, a PW signal is generated every time a data change occurs and a memory cell is selected. Then, a write operation is performed. Therefore, the time during which a memory cell is selected increases with an increase in the number of data changes, and the effect of reducing the current consumption, which is a feature of the pulse word method, is impaired. In addition, when reading from the same memory cell after writing, it is necessary to perform reading after completion of precharging of the digit line pair D and / D of the memory cell. Reading is delayed, which is an obstacle to realizing high-speed access. That is, if an address selection for the next read immediately occurs after the write, the read is performed in a state where the previous data remains on the digit line pair D and / D, which causes an erroneous read. For this reason, it is necessary to precharge the digit line pair D and / D after writing, and the next reading is delayed by the time TWR for performing the precharging, which is an obstacle to improving the access speed. become.

In recent years, a memory cell called a 4Tr memory cell without a load transistor or a load resistor has been proposed in order to miniaturize and increase the density of the memory cell. FIG. 12 shows the circuit, which includes driver transistors NMOS1 and NMOS2 composed of a pair of NMOS transistors and access transistors PMOS1 and PMOS2 composed of a pair of PMOS transistors. And the access transistor has a gate connected to the word line WL and a source / drain connected between the nodes N1 and N2 of the driver transistors NMOS1 and NMOS2 and the digit line pair D and / D. In this 4Tr memory cell, by connecting the digit line pair D and / D to the circuit power supply via the precharge circuit, the potential of the nodes N1 and N2 is held by the subthreshold leak current in the access transistors PMOS1 and PMOS2 during precharge. are doing.

When an asynchronous SRAM circuit is to be constructed using the 4Tr memory cell, a memory cell is selected at the time of writing, and one of the digit line pairs D and / D connected to the memory cell is selected. Is lowered to the GND level, the high potential node in the unselected memory cells connected to this digit line pair
, And the H data of the memory cell is destroyed. Therefore, the asynchronous SRA in which the start and the end of the data writing are controlled by the write enable signal WE.
In the M circuit, the digit line pair D and / D are GN during writing.
D level and cell data can no longer be held.
It becomes difficult to configure an asynchronous SRAM circuit with memory cells. This will be described below with reference to FIG. In FIG. 11, a pulse word is output for each data change. However, in an actual system, since the data bus is shared by a plurality of chips, a small signal change may occur during the data indefinite period. Normally, a disturb state that assumes such a case must be considered in product design and evaluation. If 1 and 0 change in a short period in the disturb state, the internal pulse words are connected to form a long pulse. This is almost the same as the word selection in the non-pulsed writing state. Here, if the period of 0 is very short relative to the period of 1 (trigger noise is assumed), most of the time transmitted to the inside becomes 1 write, so that one bit line is almost fixed to GND. State. There is no problem in the case of a 6Tr cell, but in a 4Tr cell, unselected data on this bit line is destroyed.

On the other hand, in the DRAM, precharging is performed after data writing is completed. However, since this precharging is for restoring cell data, it is necessary to sufficiently perform the precharging. Therefore, if the time TWR required for precharging after writing data is sufficiently ensured, the next read will be significantly delayed, which is an obstacle to realizing high-speed access.

An object of the present invention is to provide an SRAM circuit or a DR circuit.
It is an object of the present invention to provide a semiconductor memory device provided with any one of the AM circuits and capable of realizing high-speed access. It is another object of the present invention to provide a semiconductor memory device having an SRAM circuit, which has reduced power consumption and has an asynchronous SRAM circuit using 4Tr memory cells.

[0010]

According to the present invention, there is provided a memory circuit for selecting a memory cell based on a pulse signal generated inside the circuit and writing and reading data, and an address input in a previous write cycle. And data holding means, and means for writing the held data to a memory cell selected by the held address in a next write cycle.

For example, when the present invention is configured as an SRAM circuit, a memory cell array composed of SRAM memory cells, a means for generating a pulse word signal in response to an address change, an X address register for latching a write address, and a Y address register An address register, a data register for latching write data, and a write enable signal for causing each register to latch each address and data in a previous data write cycle and outputting the latched address and data in a next data write cycle A word line of the memory cell array is selected by the X address signal output from the X address register and the pulse word signal, and the memory cell is selected by a Y address signal output from the Y address register. Digit line pair in the array is selected, and writes the data outputted from the data register to a memory cell selected by the selected word line and the digit line pairs.

Further, when the present invention is configured as an SRAM circuit, it is configured as an SRAM circuit that selects an SRAM memory cell based on a pulse word signal generated inside the circuit and writes and reads data. Has a driver transistor consisting of a pair of NMOS transistors whose gate and drain are cross-connected, a gate connected to the word line, and a source and drain connected between the drain of each driver transistor and each of the pair of digit lines. A pair of PMOS
And an access transistor composed of a transistor.

Further, when the present invention is configured as a DRAM circuit, a memory cell array composed of DRAM memory cells, an address register circuit capable of holding a write address in a previous cycle, and the address register circuit receiving an address change Means for outputting the address held in the memory, a data register circuit for latching the write data of the previous cycle, and means for receiving the write enable signal and generating a row enable signal, a column enable signal, and a sense amplifier enable signal as pulse signals A memory cell selected by a write address of a previous cycle held in the address register circuit by the row enable signal, the column enable signal, and the sense amplifier enable signal, and stored in the data register circuit. And writes the previous cycle of the write data.

In the semiconductor memory device of the present invention, data is written and read out by a pulse signal generated inside the circuit without using an external synchronization signal, and the memory cell selected in the previous write cycle is written to the memory cell. Since data is written in the next write cycle, TWR
The time can be reduced or reduced to zero, and the access speed can be improved. Also, in the SRAM circuit, even when data change occurs a plurality of times during a long cycle write operation, the finally determined data is written by one PW signal, which is a feature of the pulse word method. The effect of reducing current consumption can be sufficiently exhibited. Further, when reading from the same memory cell after writing is performed, data before writing to the memory cell stored in the data register is simply output as read data to the output bus as it is, so that higher speed access can be realized. .

Further, when the present invention is applied to an SRAM circuit, even when the memory cell array is composed of 4Tr memory cells, data can be written in a pulse word system by writing data with one pulse signal. Reading becomes possible, and a semiconductor memory device having an asynchronous SRAM circuit using 4Tr memory cells can be realized. In addition, since a refresh operation can be performed after data is written by one pulse signal, it is possible to realize an SRAM-specific memory having a long write operation using a DRAM.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram of a first embodiment in which the present invention is applied to an SRAM circuit. The memory cell array MCA here is constituted by the 6Tr memory cells shown in FIG. 7, and the word line WL is selected by the output of the word and gate 101. A digit line pair D, / D connected to the memory cell array MCA includes a precharge equalizing circuit 102 for precharging and equalizing the digit line pair, and a plurality of MOs.
A column switch circuit 103 composed of S transistors T11 to T14 for selecting a digit line pair at the time of writing and at the time of reading is connected. The precharge equalizing circuit 102 and the column switch circuit 10 are connected to each other.
3 is selected by the output of the digit and gate 104 to select the digit line pair D and / D of the memory cell array MCA. In addition, the column switch circuit 1
03, a write amplifier circuit 105 for amplifying data to be written to a memory cell and supplying the amplified data to a digit line pair
And a sense amplifier circuit 106 for amplifying and detecting the potential difference of the memory cell output between the pair of digit lines D and / D. A data output circuit 107 is connected to the sense amplifier circuit 106 and outputs read data to the outside.

An input terminal of an X address signal for selecting the memory cell has an X address register 1 for each bit.
11 are provided. Similarly, at the input end of the Y address signal, a Y address register 112 is provided for each bit. An address signal output from the X address register 111 is input to an X decoder 113, where it is decoded and input to the word and gate 101.
The address signal output from the Y address register 112 is input to the Y decoder 114, where it is decoded and input to the digit and gate 104.
Further, an ATD signal and a Hit signal are output from each of the address registers 111 and 112. The ATD signal is input to an ATD circuit 118 described later, and the Hit signal is input to a hit and gate 119. A data register 115 is connected to the input / output terminal I / O of the data Din to be written into the memory cell. Data output from the data register 115 is input to the write amplifier circuit 105 and the data output circuit 107, respectively. In particular, data input from the data register 115 to the data output circuit 107 can be output from the data output circuit 107 to the input / output terminal I / O by the output of the hit and gate 119.

On the other hand, a read / write control circuit 116 is provided at each input terminal of the / CS signal and the / WE signal.
The read / write control circuit 116 outputs the WE1 (write enable) signal and the RW1 (read / write switching) signal when the / CS signal and / WE signal are at L level, and outputs the X address register 111 and the Y address register. 112 and the data register 115, respectively. The read / write control circuit 116 outputs an MP signal, which is a pulse generation signal, and outputs the pulse signal to the internal pulse generator 1.
17 is input. The internal pulse generator 117 outputs the ATD signal when the address is changed.
TD (address transition detector) circuit 1
An ATD signal is input from the A / D converter 18 and a PW (pulse word) signal, a BS (block select) signal, an SE (sense amplifier enable) signal, an EQ
(Equalizer) signal and WA (write amplifier activation) signal are generated.
The BS signal and the SE signal are output to the digit and gate 104, respectively. The WA signal is output to the write amplifier circuit 105. In the digit and gate 104, the EQ signal and the BS signal are respectively
Output when the Y address signal from the decoder 114 is input.

Next, the configuration of the main part of the SRAM circuit configured as described above will be described in detail. X address register 1
11 and the Y address register 112 have the same configuration, and FIG. 2 shows an example thereof. Address signal XAdd (YAd)
d) is branched into a write path 121 and a read path 122, and the write path includes a first latch 123 and a second latch 12
4 are connected in cascade, and the buffer 12
5, 126 are connected in two stages. The first latch 123 and the second latch 124 are connected to the read / write control circuit 116.
Is input to the first latch 123 and input to the second latch 124 via the inverter 127, thereby selectively and sequentially switching between the latch state and the through state. The read / write control circuit 1 is connected to the write path 121 and the read path 122, respectively.
The gates 128 and 129 which are selectively turned on at the time of writing and at the time of reading by the RW1 signal from 16 are inserted, and the outputs of these gates 128 and 129 are output as the address signal and ATD signal. Further, both address data of the write path 121 and the read path 122 are input to the hit address comparator 130, and when the outputs match, the Hit signal is output. 13
An inverter 1 inverts the RW1 signal. Since various configurations of the latch itself are widely known, a description thereof will be omitted.

Further, the data register 115 is
As shown in the example of FIG.
The latch 141 and the second latch 142 are connected in cascade, and the WE1 signal from the read / write control
Input to the latch 141 and the second
By inputting to the latch 142, the first latch 141 and the second latch 142 are selectively and sequentially switched to a latch state and a through state. And the second
The output of the latch 142 is connected to the write amplifier circuit 1
05 to the data output circuit 107 on the other hand.

The operation of writing and reading data in the SRAM circuit having the above configuration will be described. First, in the read / write control circuit 116, the / CS signal and the / WE signal are input, and as shown in FIG. 4, / CS = L at the time of address selection of the read operation and the write operation by the address signal Add, and / W when writing
When E = L, RW1 = L and WE1 = L are output. When / WE = H, RW1 = H, WE
1 = H. The WE1 signal is a signal for controlling the latches of the XY address registers 111 and 112 and the data register 115. When WE1 = L, the first latches 123 and 141 of each register are through and the second latch 12
4 and 142 are latches. Conversely, when WE1 = H, the first latches 123 and 141 are latches, and the second latches 124 and 142 are latched.
Is through. Therefore, when / WE1 = L changes, the address and data are respectively latched in the first latches 123 and 141, and when WE1 = H, the first latches 123 and 141 latch.
141 becomes through, the second latches 124 and 142 become latches, and the addresses and data of the first latches 123 and 141 are latched by the second latches 124 and 142, respectively.
Further, at the next WE1 = L, the addresses and data of the second latches 124 and 142 are output, respectively.

The RW1 signal is a read / write switching signal for each of the XY address registers 111 and 112, as shown in FIG.
The first gate 128 is turned on to output the write address latched by the second latch 124. Also, RW1
= H, the gate 129 of the read path 122 is turned on to output the read address.

On the other hand, as shown in FIG. 5, the address output from each of the XY address registers 111 and 112 is A
When input to the ATD circuit 118 as a TD signal, A
In response to the address change, the TD circuit 118 outputs an ATD signal, which is a one-shot pulse signal, which is input to the internal pulse generator 117. Internal pulse generator 1
At 17, receiving the ATD signal, the PW signal, the BS signal,
An SE signal, an EQ signal, and a WA signal are generated. in this case,
Although illustration is omitted, for example, in the generation of the PW signal, the AT
A certain pulse signal is generated from the pulse edge of the D signal by using a delay circuit, and is used as a PW signal. The same applies to the EQ signal, the BS signal, and the SE signal. Also,
Of these signals, at least a PW signal, an EQ signal,
The BS signal is generated as a synchronized signal. FIG.
Indicates that, when an address change is performed, a one-shot pulse is generated from the ATD circuit to output an EQ signal, a PW signal,
Generate BS signal, SE signal and WA signal.
As shown in (1), the PW signal must be generated even when the address change is not performed and / WE is switched to change from read to write or from write to read. When not selected (/ CS = H, / WE = L), an EQ signal, a PW signal, a BS signal, an SE signal, and a WA must be generated.

The PW signal is sent to the word and gate 101
And the X address output from the X decoder 113, outputs a WS signal as a word selection signal from the word and gate 101, selects the word line WL of the memory cell array MCA, and selects the access transistor of the selected memory cell. Is turned on. Also, the BS signal is input to the digit and gate 104, and the Y decoder 1
The digit and gate 104 output the digit selection signal BS with the Y address output from the digitizer 14 and turn off the precharge equalizing circuit 102 connected to the selected digit line pair D, / D, and the column switch circuit 10
Turn 3 on. The precharge equalizing circuit 10
2 sets the selected digit line pair to a predetermined level when it is turned on, so that the BS signal is synchronized with the PW signal, so that the digit line pair is not used except when the word line is selected. This means that charge equalization has been performed. Note that the digit selection signal BS has its H,
Depending on the state of L, the selected digit line pair is connected to either the write amplifier circuit 105 or the sense amplifier circuit 106. Further, the sense amplifier circuit 106
It is activated by the SE signal.

Next, referring to FIG.
The read operation timing will be described. The X address signal and the Y address signal are stored in each address register 1 respectively.
11 and 112, and the WE1 signal and the RW1 signal from the read / write control circuit 116 to which the / CS signal and the / WE signal are input.
23 and held by the WE1 signal generated by the / WE signal by the latch in the second latch 124 (rate)
Is done. On the other hand, it is not latched at the time of reading. Similarly, Din input in the data register 115 includes the first and second latches 141 and 141.
It is held by the latch at 142. Further, the ATD signal is output from the ATD circuit 118 based on the ATD signal output from each of the address registers 111 and 112, so that the PW signal, the BS signal, and the EQ are output from the internal pulse generator 117 even without an address change. A signal and an SE signal are output. Therefore, at the time of reading, / CS =
At L, a PW signal is generated by an address change, a word line is selected, a digit line pair connected to the sense amplifier circuit 106 is selected by the column switch circuit 103, and the precharge equalize circuit 102 is turned off by the EQ signal. As a result, a memory cell is selected, and data of the memory cell is read out to the data output circuit 107 through the digit line pair D and / D. This read operation is the same as the conventional pulse word method.

On the other hand, at the time of writing, paying attention to the write cycle of address A1, address change occurs, and / C
When S = L and / WE = L, an address is input to the address registers 111 and 112, and data Din is input to the data register 115. The first and second latches 123, 124,141,1
As a result, at the timing when / WE = H, the address is latched by the address registers 111 and 112, and the data is latched by the data register 115. Then, at the next edge of / WE = L, each of the registers 111, 112, 1
15 and outputs the latched address and data. In response to the output of the address, the address is input from the X decoder 113 to the word and gate 101, the word line is selected in synchronization with the PW signal, and the Y address is input from the Y decoder 114 to the digit and gate 104,
A digit line pair D, /, which is connected to the write amplifier circuit 105 by selecting the column switch circuit 103 according to the BS signal.
D and the precharge equalizing circuit 102
Is turned off, and the write amplifier circuit 105 is activated. Thereby, data is written to the selected memory cell. That is, data is written to the memory cell at a timing one delay later than the PW signal generated at the time of writing, so that a so-called rate write SRAM circuit is configured. Thereby, for example, the long write cycle A shown in FIG.
Even when data 1, data 2 and data 3 of a plurality of data changes occur in 1, the last data 3 is latched in the data register at the time of writing, and the latched data is written by the PW signal A1 at the next writing. Therefore, one PW signal can cope with a data change, thereby preventing an increase in current consumption due to generation of a plurality of PW signals as in the related art.

Further, in the SRAM circuit of the above embodiment,
The write address is latched and held in each of the XY address registers 111 and 112, and the next read address is compared with the next read address in the hit address comparator 130. When both match, the hit-and-gate 119 switches from Hi to Hi.
The t signal is output. Further, the data register 115 latches and holds the write data, outputs the data at the timing of the next read, and outputs the data in the data output circuit 10.
Enter 7 Therefore, at the time of a so-called hit read in which the write address matches the read address, data that has not been written to the memory cell can be read from the data output circuit 107 as it is, and a higher read speed can be realized.

The above description is an embodiment in which a memory cell is applied to a 6Tr memory cell, but the 4T memory cell shown in FIG.
The same can be applied to the r memory cell. In particular, when the 4Tr memory cell has a long memory cell selection time during writing, that is, a long writing cycle time,
The data is lowered to the GDN level, and the H data of the unselected memory cell is destroyed through the digit line. Therefore,
4Tr is used as a memory cell of the SRAM circuit of the embodiment.
By applying the memory access, an asynchronous SRAM circuit in which the data of the 4Tr memory cell is not destroyed can be configured.

As described above, the asynchronous SRAM circuit using the 4Tr memory cell, which has been difficult to realize in the past, is replaced with the rate write SR circuit using the pulse word system.
This can be realized by configuring as an AM circuit. In this case, by adopting a circuit configuration that does not perform latching in the address register and the data register having the configuration shown in FIG. 1, a pulse word type SRAM circuit which is not a rate write type can be configured.

Next, the second embodiment in which the present invention is applied to a DRAM circuit will be described.
An embodiment will be described. FIG. 13 is a block circuit diagram of the DRAM circuit. In the memory cell array 201, a word line and a bit line are extended in the row direction and the column direction, respectively.
Memory cells each composed of a transistor and a capacitor are arranged in a matrix. The memory cell array includes a row decoder 202, a sense amplifier / reset circuit 203,
A column decoder 204 is provided. As described later in detail, the word line is selected by the row decoder 202, and the bit line is selected by the sense amplifier / reset circuit 2.
03 and the column decoder 204 select a memory cell to perform writing, reading, precharging, or refreshing. The row decoder 202 decodes the address M-ADD when a row enable signal RE from a row control circuit 214, which will be described later, is at an H level.
Activate the word line specified by ADD. When a column enable signal from a column control circuit 215 to be described later is at H level, the column decoder 204
ADD is decoded, and a bit line specified by the address L-ADD is selected.

The sense amplifier / reset circuit 203
Although not shown in the figure, is composed of a sense amplifier, a column switch, and a precharge circuit. The column switch connects the sense amplifier designated by the column selection signal output from the column decoder 204 to the bus WRB. When the sense amplifier enable signal SE is at the H level, the sense amplifier detects and amplifies the potential of the bit line connected to the memory cell specified by the address Add and outputs it to the bus WRB, or is supplied to the bus WRB. The written data is written to the memory cell via the bit line. The precharge circuit precharges the potential of the bit line to a predetermined potential, for example, 電位 of the power supply potential, when the precharge enable signal PE is at the H level.

On the other hand, the address buffer 205 buffers an externally input address and outputs it to the address register circuit 206. The address register circuit 206 multiplexes the input address L-ADD into a multiplexer (M
UX) 207. Also, the address Add input at the falling edge of the control signal LW1 is held in a built-in register (not shown). Further, when the control signal LW1 is at the H level, the address held in the internal register is output as the address L-ADD. Further, the address register circuit 206 receives the input address Add.
And a comparator for comparing an address held in a built-in register, and outputs a hit signal HIT as an H level when they match.

The ATD circuit 208 receives the chip select signal / CS and the address Add and inputs the address Add when the chip select signal / CS is valid (L level).
When d changes, that is, when the address changes, the address change detection signal ATD is output as a one-shot pulse. Further, the refresh control circuit 209
The address change detection signal ATD and the write enable signal / WE are input, and based on these signals, refresh control signals REFA and REFB are output, and simultaneously, a refresh address R-ADD is output to the multiplexer 207, and the memory cell array The memory cell 201 is refreshed.

The multiplexer 207 receives the address change detection signal ATD and the refresh control signal REF.
B, and the refresh address R- from the refresh control circuit 209 is supplied according to the state of these signals.
ADD or the address L-ADD from the address register circuit 206 to select the address M-
ADD is output to the row decoder 202. In particular, when the address change detection signal ATD is at the H level, that is, when an address change occurs, the address L-AD
Select and output D.

The hit control circuit 210 takes in the hit signal HIT at the rise of the address change detection signal ATD, and outputs this as a hit enable signal HE to the data register circuit 211. Data register circuit 211
Is externally connected to the bus WRB through the I / O buffer 212 with the falling edge of the control signal LW2 as a trigger.
X is fetched into a built-in data register (not shown),
Output to When the control signal LW2 is at H level, the data register circuit 211 outputs the write data fetched into the built-in data register to WRB. When the control signal LW2 is at the L level, different operations are performed according to the hit enable signal HE. That is, when the hit enable signal HE is at the L level, the read data on the bus WRB is output to the bus WRBX. When the hit enable signal HE is at the H level, write data not written in the memory cell array 201 is output on the bus WRBX. The I / O buffer 21
2 is the bus WRB when the control signal CWO is at the H level.
The read data on X is output to the outside. Further, when the control signal CWO is at the L level, external write data is output to the bus WRBX.

R / W (read / write) control circuit 213
Is a control signal C based on a chip select signal / CS, a write enable signal / WE, and an output enable signal OE.
WO, LW1, and LW2 are generated.

The row control circuit 214 includes refresh control signals REFA, REFB and an address change detection signal A.
Based on TD and write enable signal / WE, row enable signal RE, sense amplifier enable signal S
E, precharge enable signal PE, and control signal C
Output C. That is, the row control circuit 214
The row enable signal RE is generated as a one-shot pulse with the rising edge of the address change detection signal ATD as a trigger. The row enable signal RE is delayed to generate a sense amplifier enable signal SE. Further, when the refresh control signal REFB is received,
As a one-shot pulse, a row enable signal RE, a delayed precharge enable signal PE and a sense amplifier enable signal SE are generated. The width of the one-shot pulse of the row enable signal RE is set to a pulse width sufficient to perform writing and reading. Further, the row control circuit 214 generates a control signal CC by delaying the row enable signal RE. The column control circuit 215 outputs the delayed control signal C
The column enable signal CE is generated by further delaying C. That is, a column enable signal CE is generated as a one-shot pulse. Here, the row enable signal RE and the column enable signal CE as the one-shot pulse correspond to the pulse word signal PW of the first embodiment.

The operation of the DRAM circuit having the above configuration is shown in FIG.
This will be described with reference to the timing chart of FIG. The address A (W) is input from the address buffer 205 to the address register circuit 206 as the address Add, and further input to the multiplexer 207, and the multiplexer 207 outputs the address A (W) as the address M-ADD. At this time, the address A (W-1) of the previous cycle is held in the address register circuit 206. When the address change detection signal ATD goes high in response to the change in the address A (W) and the write enable signal / WE falls, the multiplexer 207 sets the address M-ADD to the address L-ADD, that is, the address M-ADD.
The address is switched to the address A (W-1) of the previous cycle held in the address register circuit 206. In response to the fall of the write enable signal / WE, the row control circuit 214 outputs a row enable signal RE and a sense amplifier enable signal SE as one-shot pulses, and further generates a control signal CC.
15 outputs a column enable signal CE. On the other hand, the R / W control circuit 213 which has received the write enable signal / WE receives the control signal LW2 and takes in the data Din of the previous cycle which is taken into the data register circuit 211.
(W-1) is supplied to the bus WRB.

Therefore, the word line at the address A (W-1) of the memory cell is selected by the row decoder 202 in response to the rise of the row enable signal RE, and subsequently the column decoder 204 in response to the rise of the column enable signal CE. Address A of memory cell array
The sense amplifier of the sense amplifier / reset circuit 203 corresponding to the bit line (W-1) is selected and connected to the bus WRB. As a result, the data D is stored in the memory cell corresponding to the address A (W-1) through the sense amplifier.
in (W-1) is written. In other words, address A
When dd is the write cycle of A (W), the data Din (W-W-) of the previous cycle is stored in the address A (W-1) of the previous cycle.
1) is written with a delay. That is, rate writing is performed.

After the rate write is performed, a time corresponding to the pulse width of the one-shot pulse elapses.
A row enable signal RE, a column enable signal CE,
When the sense amplifier enable signal SE falls, the multiplexer outputs A (W) as the address M-ADD. After the rate write, a precharge enable signal PE not shown in FIG.
Precharge is performed, but the description is omitted here. Further, after a predetermined time has elapsed from the change of the address Add, the data of the bus WRBX input to the data register circuit 211 becomes the next data Din (W). Then, the data Din (W) is taken into the built-in data register of the data register circuit 211 at the rise of the write enable signal / WE.

Here, after the completion of the rate write and during the data fetch into the data register circuit 211, the row enable signal RE is generated as a one-shot pulse in response to the refresh control signal REFB, and the delay is delayed. Then, a sense amplifier enable signal SE is generated as a one-shot pulse. Upon receiving the refresh control signal REFB, the multiplexer sets the refresh address A (f) as the address M-ADD.
Is output. Thereby, the memory cell array 201
The refresh operation is performed on the memory cell selected by the refresh address A (f). When the row enable signal RE and the sense amplifier enable signal SE fall, the multiplexer address M-ADD is output.
Becomes the address A (w) again. Note that an external refresh start trigger signal may be input instead of the refresh control signal REFB.

Next, the next read cycle is described in the timing chart of FIG. 14, and even if the address A (W) changes to A (R) and the address change detection signal ATD rises due to this address change, Since the write enable signal / WE does not fall, the multiplexer 20
7 address M-ADD is the address register circuit 206
Address A, not the address held in
(R). Then, a row enable signal RE, a column enable signal CE, and a sense amplifier enable signal S
In response to the rising edge of E, the data Dout (R) of the selected memory cell is read onto the bus WRB. When the hit enable signal HE is output from the hit control circuit 210 at the time of reading, data not written in the memory cell array 201 is output from the data register circuit 211 as it is to improve the reading speed. This is the same as the embodiment.

As described above, in the second embodiment, the row enable signal RE as a one-shot pulse and the column as a signal equivalent to the pulse word signal of the first embodiment are generated by the write enable signal / WE. An enable signal CE and a sense amplifier enable signal SE are generated, and a rate write is executed based on these signals. Therefore, the rate write can be performed at the beginning of the write cycle, and the precharge and the refresh can be performed in the write cycle immediately after that. Therefore, even when the next cycle is a read cycle, a time margin can be ensured before data is read out to the bus WRB, and an address change in the next read cycle is ensured from the end of the write cycle. The time TWR to be performed can be reduced or set to zero. Thereby, an increase in access speed is realized.

Here, for comparison, FIG. 15 shows a timing chart of the operation of the conventional DRAM without performing the rate write. In this operation, when the address Add changes to A (W), the address corresponding to the address M-ADD of the row decoder 202 also becomes A (W). When the write enable signal / WE falls, the row enable signal R
E, a column enable signal CE, and a sense amplifier enable signal SE rise to select a memory cell. Then, after the data Din (W) is output from the data register circuit 211 to the bus WRB, the data is written to the selected memory cell at the rising timing of the write enable signal / WE. Further, after this writing, a precharge is executed. When the next cycle is a read cycle, the bus WRB
In order to secure time until data is read out, it is necessary to secure at least the time TWR necessary for precharge between the end of the write cycle and the address change in the next read cycle. Further, when performing refresh, it is necessary to secure a time TWR including a time required for the refresh. Therefore, the increase in the access speed is hindered by the time TWR.

As can be seen from the description of the second embodiment, even when the present invention is applied to a DRAM, in a given cycle of a write request, a given write address and write data are fetched and held. Then, in the next cycle in which a write request is input,
Since the write data is written to the held write address, by writing at the beginning of the cycle, it is possible to perform precharge or refresh after writing in the cycle, and until the address change of the next read cycle. The time TWR of
Alternatively, it can be set to 0, and the access speed can be improved.

[0046]

As described above, according to the present invention, data is written and read out by an asynchronous system without using an external synchronization signal, and a pulse signal generated inside the circuit, and data is selected in a previous write cycle. Since the rate write method of writing data to the memory cell in the next write cycle is adopted, the TWR time can be reduced and the access speed can be improved even when the next read cycle comes. . In particular, in the present invention, in the case where the writing using the asynchronous pulse word signal is employed in the SRAM circuit, even if the data change occurs a plurality of times during the long cycle write operation, the finally determined data is not written. The writing operation can be performed by one pulse word signal, and the effect of reducing current consumption, which is a feature of the pulse word method, can be sufficiently exhibited. In addition, the present invention provides an SRA
In both the M circuit and the DRAM circuit, when reading from the same memory cell after writing,
Since data before writing to the memory cell can be read, further high-speed access can be realized. further,
In the SRAM circuit configured according to the present invention, even when the memory cell array is configured by 4Tr memory cells, data can be written and read by the pulse word method.
An asynchronous SRAM circuit using Tr memory cells can be realized. That is, since pulse writing can be performed once, an asynchronous SRAM circuit using 4Tr cells can be realized. Furthermore, after one pulse write, a refresh operation can be performed if necessary.
It becomes possible to realize a memory of the AM specification by a DRAM cell.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an overall configuration of a first embodiment in which a semiconductor memory device of the present invention is applied to an SRAM circuit.

FIG. 2 is a block circuit diagram showing a configuration of an address register.

FIG. 3 is a block circuit diagram showing a configuration of a data register.

FIG. 4 is a timing chart for explaining a pulse generation operation in a read / write control circuit;

FIG. 5 is a timing chart for explaining a pulse generation operation when an address change occurs in an internal pulse generation circuit.

FIG. 6 is a timing chart for explaining a pulse generation operation when there is no address change in the internal pulse generation circuit.

FIG. 7 is a timing chart for explaining write and read operations by a pulse word type rate write in the SRAM circuit of FIG. 1;

FIG. 8 is a timing chart for explaining particularly a long write operation of the rate write.

FIG. 9 is a circuit diagram of an example of a 6Tr memory cell.

FIG. 10 is a timing chart for explaining the operation of the conventional asynchronous system.

FIG. 11 is a timing chart for explaining the operation of the conventional pulse word system.

FIG. 12 is a circuit diagram of an example of a 4Tr memory cell.

FIG. 13 is a block circuit diagram of an overall configuration of a second embodiment in which the present invention is applied to a DRAM circuit.

FIG. 14 is a timing chart for explaining write and read operations in the DRAM circuit of FIG. 13;

FIG. 15 is a timing chart for explaining a conventional write / read operation in the DRAM circuit of FIG. 13;

[Explanation of symbols]

 Reference Signs List 101 word and gate 102 precharge equalize circuit 103 column switch circuit 104 digit and gate 105 write amplifier 106 sense amplifier 107 data output circuit 111 X address register 112 Y address register 113 X decoder 114 Y decoder 115 data register 116 read / write control circuit 117 Internal pulse generation circuit 118 ATD circuit 119 Hit and gate 123, 141 First latch 124, 142 Second latch 130 Hit address comparator 201 Memory cell array 202 Row decoder 203 Sense amplifier / reset circuit 204 Column decoder 205 Address buffer 206 Address register Circuit 207 Multiplexer 208 ATD circuit 209 Refresh control circuit 210 Hit control circuit 211 Data register circuit 212 I / O buffer 213 R / W control circuit 214 Row control circuit 215 Column control circuit

Claims (9)

[Claims] 1. A semiconductor memory device that selects a memory cell based on a pulse signal generated inside a circuit and performs data writing and reading, and holds an address and data input in a previous writing cycle. And a means for writing the held data to a memory cell selected by the held address in a next write cycle. 2. A memory cell array comprising SRAM memory cells, means for generating a pulse word signal in response to an address change, an X address register and a Y address register for latching a write address, and data for latching write data A register and a means for latching each address and data in each register in a previous data write cycle and generating a write enable signal for outputting the latched address and data in a next data write cycle; A word line of the memory cell array is selected by the X address signal output from the address register and the pulse word signal,
A digit line pair of the memory cell array is selected by a Y address signal output from the Y address register, and data output from the data register is written to a memory cell selected by the selected word line and digit line pair. A semiconductor memory device characterized by the following. 3. The SRAM memory cell includes a pair of driver transistors having gates and drains cross-connected, a gate connected to a word line, a source and a drain connected to the drain of each driver transistor, and a pair of digit lines. 3. The semiconductor memory according to claim 2, comprising a pair of access transistors connected therebetween, and a load transistor or a load resistor connected between a drain of each of the driver transistors and a power supply. apparatus. 4. The SRAM memory cell includes a driver transistor including a pair of NMOS transistors whose gates and drains are cross-connected, a pair of digits having a gate connected to a word line and a source and a drain connected to the drain of each driver transistor. 3. An access transistor comprising a pair of PMOS transistors connected between each of the lines.
Or the semiconductor memory device according to 3. 5. An SRAM circuit for selecting an SRAM memory cell based on a pulse word signal generated inside the circuit and writing and reading data,
The memory cell includes a driver transistor including a pair of NMOS transistors having a gate and a drain cross-connected, a gate connected to a word line, and a source and a drain connected between the drain of each driver transistor and each of a pair of digit lines. And an access transistor including a pair of PMOS transistors. 6. A memory cell array composed of DRAM memory cells, an address register circuit capable of holding a write address in a previous write cycle, and means for receiving an address change and outputting the address held in the address register circuit. A data register circuit for latching write data of a previous write cycle, and a means for receiving a write enable signal and generating a row enable signal and a column enable signal as pulse signals, and in the next write cycle, The write data of the previous write cycle held in the data register circuit is written to the memory cell selected by the write address of the previous write cycle held in the address register circuit by the signal and the column enable signal. A semiconductor memory device characterized by having the following configuration. 7. The memory device according to claim 6, further comprising means for generating a precharge enable signal in response to the write enable signal, wherein the memory cell is precharged by the precharge enable signal. Semiconductor storage device. 8. The semiconductor memory device according to claim 1, wherein data is written in response to one pulse signal. 9. A data processing apparatus comprising: means for comparing the match between a previous write address and a read address immediately after the write address; and outputting the data held by the data register when the write address matches the read address. 9. The semiconductor memory device according to claim 1, wherein: