JPH0478092A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To successively enable a serial access in a low address direction by dividing a selective word line into the plural one, and allowing the word line group whose serial access is completed to select the next low address. CONSTITUTION:A sense amplifier 5, I/O control 6, and memory cell group 11 are bisected, for example, and the serial access is operated by a column access generated inside by a clock generator circuit 1. Like this, a serial access mode is equipped with a function which changes the word line by the column address generated inside, and the mode changes the word line of the group whose access of the column address is completed into the next address. Thus, the serial access can be successively executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial access mode of a semiconductor memory device, particularly a DRAM.

[Conventional technology]

Figure 3 shows a DRA with conventional serial access mode.
It is a block diagram of M.

In the figure, Vcc is the power supply voltage, Vss is the ground level,
A, ~A9 are address input signals for selecting internal memory cells, DQ+~DQa are data output signals, and RAS, CAS, W, and OE are for determining the operation mode. Input number 3, (1) is a clock generator circuit that determines the operation mode based on RAS and CAS control signals, (2) is an address buffer that takes in address input signals, and (3) is a row decoder that selects a word line. , (4) is a column decoder that selects the hit line,
(5) is a sense amplifier that amplifies the information of the selected memory cell; (6) is an I10 control that controls reading and writing to the memory cell; (7) is a data in buffer that takes in data input; (8) ) is a data out buffer that outputs the read data, (11)
is a memory cell group.

Next, the operation will be explained. When a serial access mode is used in a conventional DRAM, when the signal RAS changes from "H" to "L", the ROW address is loaded into the address buffer (2), one row decoder (3) is selected, and the word line is , and transmits the information of the memory cell (11) to the bit line.

Next, change the signal CAS from "H" to "L", take the first COL address into the address buffer (2),
The column decoder (4) of the selected column address is selected, and the memory cell information amplified by the sense amplifier (5) is read out. Next, when the signal RAS is kept at "L" and the signal CAS is changed from "L" to "H" to "L", the column address advances by one and the next column address is selected. Thereafter, by controlling the signal CAS, the next address is accessed without manually inputting the address from the outside, and a read or write operation is performed.

This mode in which a certain row address is selected, the first column address is selected, and the next address is internally advanced and selected without manually inputting the address is called serial access mode.

Figure 4 is a timing waveform diagram showing the output state of the circuit in Figure 3 during serial access read. One piece of data, which is the data of the memory cell, is output. In the next CAS cycle, the column address advances by one, and the data at the next column address is data 2, or the data at the next CAS cycle is data 3. output the data serially.

[Invention or problem to be solved]

The serial access mode of conventional semiconductor storage devices is configured as described above, so when performing serial access across multiple row addresses, it is necessary to disconnect the serial access mode in order to select the next row address. There were problems in that row addresses had to be input manually from outside, and column addresses, which were automatically generated internally, had to be managed externally.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that allows continuous serial access once a row address and a column address are specified.

(Means for Solving the Problems) In the serial access mode of the DRAM according to the present invention, the selected word line is divided into a plurality of parts, and the word line group for which serial access has been completed selects the next row address. With this structure, continuous serial access is possible also in the row address direction.

Furthermore, by configuring the DRAM so that refresh operations necessary for the DRAM are automatically performed internally, serial access becomes possible permanently without the need to consider external refresh operations.

[Effect]

The serial access mode in this invention has the function of changing the word line using an internally generated column address, and by changing the word line of the group whose column address has been accessed to the next address, the serial access mode Access is possible.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a DRAM having a serial access mode, which is an embodiment of the present invention, and includes a sense amplifier (5), an I10 control (6), and
and shows the case where the memory cell group (11) is divided into two.

In the figure, Vcc is the power supply voltage, Vss is the ground level,
Ao-A9 is an address input signal for selecting an internal memory cell, DQr-DQ4 are data input/output signals,
The four signals RAS, CAS, W, and OE are input signals for determining the operating mode. (1) is a clock generator circuit that determines the operating mode by the control signals of RAS and CAS, and (2) is the internal address input signal. (3) is a row decoder that selects a word line, (4) is a column decoder that selects a bit line, (5)
is a sense amplifier that amplifies the information of the selected memory cell, (6) is the I10 control that controls reading and writing to the memory cell, (7) is the input buffer that takes the data internally, and (8) is the read A data out buffer outputs the output data, (9) is an internal row address control circuit that receives an internally generated column address and increments the row address, and (10) automatically refreshes during serial access mode. The auto-refresh control circuit for performing this is a memory cell group.

FIG. 2 is a timing waveform diagram showing the output state of the circuit shown in FIG. 1 during read of serial access.

Note that although the above embodiment shows the case where the word line is divided into two to perform row address control, the same effect can be obtained even if the word line is divided into three or more.

In addition, in the second embodiment, the clock generator circuit (1
) has explained the case where serial access is performed using an internally generated column address. In the case of a serial access mote that exchanges data, the word line of the memory cell group (+1) is divided into multiple parts, row addresses are controlled, and data is exchanged with the serial access memory. A RAM serial access mode has a similar effect.

(Effects of the Invention) As described above, according to the present invention, the DRAM serial access mode has the advantage that serial access can be performed continuously.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a DRAM according to an embodiment of the present invention, and FIG. 2 is a serial access read diagram of the circuit of FIG.
Figure 3 is a block diagram of a conventional DRAM, Figure 4 is a serial access Re of the circuit in Figure 3.
It is a timing waveform diagram at the time of ad. In the figure, (1) is a clock generator circuit, (2
) is the address buffer, (3) is the row decoder, (4)
is a column tecoder, (5) is a sense amplifier, (6) is an I
10 controls, (7) data in buffer, (8
) is a data out buffer, (9) is an internal row address control circuit, (10) is an auto-refresh control circuit, (
11) shows a memory cell group. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1

Claims (1)

[Claims] A semiconductor memory device having a function of serially accessing addresses, wherein once a ROW address is set, the next address is continuously accessed without refreshing or setting the ROW address.