JPH10255468A - Refresh device for dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption further without performing a refresh operation for a memory cell region being not required to hold data in a refresh device of a DRAM having a self-refresh function. SOLUTION: The last row address 512 corresponding to a memory cell region, in which refresh of memory data is required is latched to a row address latch register 14, gates G0-G10223 are gate-controlled corresponding to this latch row address. Since a refresh signal from a refresh original signal generating circuit 22 is successively supplied for only row address lines (Row Add 0, Row Add 1,...Row Add 511) corresponding to the latch row address 512 as count operation of a 10 bits counter 21, surplus power consumption accompanied by self-refresh can be eliminated without performing refresh operation for a memory region, in which data holding is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM refresh device having a self-refresh function.

[0002]

2. Description of the Related Art RAs mounted on recent electronic information devices and the like
As M, a DRAM having a self-refresh function in which a refresh circuit for a memory cell is mounted in a conventional DRAM chip is widely used.

A DR having a self-refresh function
AM stands for RAS (Row Address Select), CAS (Column
Address Select) is set to the active state for a certain period of time or more, so that memory refresh is performed according to the counter operation in the internal circuit. No external refresh operation is required. This has the advantage that the circuit design can be simplified.

[0004]

However, DRA
The storage capacity of M has recently been steadily increasing, and the current consumption associated with self-refresh also increases in direct proportion.
The self-refresh current of the RAM is 16M (mega) D
The self-refresh current of the RAM is four times as large, and there is a problem that power consumption for memory backup increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is possible to further reduce power consumption without performing a refresh operation on a memory cell area that does not need to hold data. It is an object of the present invention to provide a DRAM refresh device.

[0006]

That is, a refresh device for a DRAM according to the present invention comprises a refresh range storing means for storing a self-refresh range of a memory cell region in a DRAM, and a self-refresh range stored in the refresh range storing means. Refresh signal supply means for supplying a refresh signal to memory cells in a range to be refreshed.

That is, in the DRAM refresh device according to the present invention, the self-refresh range of the memory cell area in the DRAM is stored, and the refresh signal is supplied to the memory cells in the stored self-refresh range. For example, address data at the boundary between the area where data is being stored and the area where data is not stored in the memory cell area is latched and stored, and at the time of memory refresh, a refresh signal is supplied to memory cells subsequent to this storage address. By limiting, unnecessary refresh operations can be omitted.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an internal configuration of a DRAM having a self-refresh function equipped with a DRAM refresh device according to an embodiment of the present invention.

Each row address line (Row A) of the DRAM
dd 0, Row Add 1,…) and each Column address line
(Column 0, 1,...) At each intersection position, memory cells 11,... For holding 1-bit data are individually connected, and each row address line (Row Add 0, Row Add 1,
..) Are sequentially supplied by the refresh counter 12 via the sense amplifiers 13,.
Are rewritten (refreshed) and held.

Here, the refresh counter 12 stores a row address corresponding to the last address of the area requiring refresh in the area of the memory cells 11,... From the row address latch register 14.
Address data is supplied, and supply of a refresh signal from the row address data to a row address line corresponding to an area where refreshing is unnecessary is stopped.

That is, the Row corresponding to the maximum memory address associated with writing data to the DRAM.
The address is latched in the row address latch register 14, and a refresh signal from the refresh counter 12 is not generated in a range exceeding the row address latched in the row address latch register 14.

FIG. 2 is a timing chart showing a refresh operation of the DRAM having the self-refresh function. FIG. 3 is a diagram showing a configuration of a refresh signal supply circuit in the DRAM having the self-refresh function.

The refresh signal supply circuit in FIG. 3 has 1024 Row address lines (Row Add 0, Row).
A refresh signal (Refresh 0, Refresh 1,..., Refresh 1023) can be sequentially supplied to Add 1,..., Row Add 1023). 128
1 to count "1024" sequentially during a fixed time of ms
A 0-bit counter 21 is provided, and the 1024 Row address lines (Row Add 0, Row Add 1,..., Row) are provided in accordance with individual count data from “0” to “1023” by the 10-bit counter 21. Add 1023) is supplied from the refresh source signal generation circuit (sense amplifier 13) 22 to the corresponding gate circuit G
0 to G1023.

On the other hand, the Row address latch register 14
The row address corresponding to the final address of the memory cell area requiring refresh latched by
3 and the decoder 23 causes the latch R
Gate ON for gate control line before ow address
, And a gate-off control signal "0" is output to the gate control line after the latch Row address.

That is, the memory cell area of this DRAM is refreshed by the refresh signal (Refresh 0, Refresh 1,...) Up to the area corresponding to the Row address latched by the Row address latch register 14. .

That is, when writing data to the DRAM, the maximum write address is, for example, "512".
In the case where data is stored only in the first half area of the memory cell area and no data is stored in the second half area, the Row address latch register 14 stores the Row address “512”. Is stored.

Then, the decoder 23 controls the gates G0 to G0.
The control signal "1" for turning on the gate is output only to G511, and only for Row address lines (Row Add 0, Row Add 1,..., Row Add 511) for a fixed time (128 ms). In accordance with the count data "0" to "511" of the bit counter 21, the refresh signal from the refresh source signal generation circuit (sense amplifier 13) 22 is sequentially supplied via the corresponding gate circuits G0 to G511.

As a result, the refresh signal is supplied only to the memory cell area in which data is written, and it is possible to suppress extra power consumption accompanying the memory refresh.

That is, the DRAM used in this embodiment
If the storage capacity of the memory is, for example, a 2 Mbyte DRAM, it is not necessary to perform a refresh operation on the latter half area that does not need to hold data. The current can be reduced by half.

Therefore, according to the DRAM having the self-refresh function having the above-described configuration, the final row corresponding to the memory cell region where the memory data needs to be refreshed.
Address “512” is stored in the row address latch register 1
4 and the gates G0 to G1023 are gate-controlled in accordance with the latched Row address. With the count operation of the 10-bit counter 21, the refresh signal from the refresh source signal generation circuit (sense amplifier 13) 22 Row Address lines (Row Add 0, Row Add 1,..., Row A) corresponding to the latch Row address “512”
dd 511), so that unnecessary power consumption associated with self-refresh can be eliminated without performing a refresh operation on a memory area that does not require data retention.

In the above embodiment, one DRAM is used.
In the memory cell area in the area, the area that needs to be refreshed and the area that does not need to be refreshed are divided by Row addresses.
Ro to which refresh signal is supplied at the address boundary
Although the w address line is configured to be gate-controlled, when a plurality of DRAMs are used, the necessity of refresh /
It is also possible to adopt a configuration in which the unnecessary state is controlled in individual DRAM units.

FIG. 4 shows a DR according to another embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a DRAM having a self-refresh function equipped with an AM refresh device. In other words, in a memory device using a plurality of DRAMs 1 to 4, a configuration is adopted in which a refresh signal from the refresh control unit 31 is supplied in parallel to each of the DRAMs 1 to 4, and a DRAM that does not require memory refresh is provided.
By selectively stopping the supply of power to the RAM 3 and the DRAM 4 by the DRAM selection power supply control unit 32,
It is possible to reduce the power consumption accompanying unnecessary memory refresh.

[0023]

As described above, the DRAM according to the present invention is described.
According to the refresh device of the first aspect, the self-refresh range of the memory cell region in the DRAM is stored, and a refresh signal is supplied to the memory cells in the stored self-refresh range. Address data at the boundary between the middle area and the area where data is not stored is latched and stored, and at the time of memory refresh, unnecessary refreshing is restricted by restricting the supply of refresh signals to memory cells subsequent to the storage address. Operation can be omitted. Therefore, it is possible to further reduce power consumption without performing a refresh operation on a memory cell region that does not need to hold data.

[Brief description of the drawings]

FIG. 1 shows a DRAM having a self-refresh function equipped with a DRAM refresh device according to an embodiment of the present invention.
FIG. 2 is a diagram showing an internal configuration of a RAM.

FIG. 2 is a DRAM having the self-refresh function.
5 is a timing chart showing the refresh operation of FIG.

FIG. 3 is a DRAM having the self-refresh function;
FIG. 3 is a diagram showing a configuration of a refresh signal supply circuit in FIG.

FIG. 4 is a diagram showing a configuration of a DRAM having a self-refresh function equipped with a DRAM refresh device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Memory cell, 12 ... Refresh counter, 13 ... Sense amplifier, 14 ... Row address latch register, 21 ... 10-bit counter, 22 ... Refresh source signal generation circuit, 23 ... Decoder, Refresh0-Refresh 1023 ... Refresh signal, G 0 to G1023: Refresh signal output gate.

Claims (2)

[Claims] 1. A DRA having a self-refresh function
M refresh device, comprising: refresh range storage means for storing a self-refresh range of a memory cell area in a DRAM; and a refresh signal supplied to the memory cells in the self-refresh range stored in the refresh range storage means. And a refresh signal supply means. 2. The refresh range storage means includes:
A register for latching a row address in a self-refresh range of a memory cell area in the AM; a refresh signal supply unit for supplying a refresh signal to a memory cell of each row address in the DRAM; Gate means for passing a refresh signal for each row address of the DRAM generated by the means, and gate control means for controlling the gate means according to the row address latched in the register. A refresh device for a DRAM according to claim 1.