JP2000235789A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent wasteful power consumption and reduction of a bandwidth due to excessive refreshes by allowing this controller to have a refresh counter counting a cycle shorter than a refresh cycle which is stipulated in a DRAM and an address storage circuit storing addresses accessed in a fixed time and performing refreshes while excluding these addresses. SOLUTION: When data access is not performed, a timing control circuit 2 performs collective refreshes in the proportion of one time to two times of a timing signal which is to be outputted by a refresh counter 4 and whose cycle is 1/2 of a refresh cycle (tREF) which is stipulated in the DRAM. When data access is performed during tREF/2 just before the collective refreshes are to be performed, a Row address storage circuit 5 stores these Row addresses. The timing control circuit 2 performs refreshes by excluding refreshes of these Row addresses at the time of performing the collective refreshes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a memory that requires periodic refreshing to hold data stored in a memory cell.

[0002]

2. Description of the Related Art Due to their functions, memories are mainly ROM (R
ead Only Memory) and RAM (Rand)
om Access Memory). Furthermore, RAM is roughly classified into SRAM (St)
atomic RAM) and DRAM (Dynamic RA)
M). A DRAM is suitable for high integration because of a simple memory structure including two elements, one transistor and one capacitor, and can be realized at a lower price than an SRAM. For this reason, it is widely used in main memories or image memories of personal computers, workstations, large computers, and the like.

Since information in a DRAM memory cell is stored as an electric charge in a capacitor, it needs to be rewritten (refreshed) within a predetermined time. The DRAM is refreshed by accessing all the word lines within a specified time tREF (refresh cycle).
The refresh cycle tREF and the number of word lines (corresponding to the number of refresh cycles) are determined depending on the product type. For example, a 4 Mbit D having a data bus width of 16 bits
In the RAM, it is necessary to perform 512 refresh cycles within 8 ms.

[0004] As a method of executing this refresh cycle, a concentrated refresh method in which refresh is continuously performed every tREF (8 ms) and a method of performing tREF (8 ms) /
There is a distributed refresh method in which one cycle is performed every 512 ≒ 15.6 μs. FIG. 5A is a timing chart of the centralized refresh method, and FIG. 5B is a timing chart of the distributed refresh method.

Further, each refresh method includes a RAS only refresh in which a refresh is performed by inputting a Row address in synchronization with a RAS (Row Address Strobe), and a CAS (Col).
a CAS before RAS, a CAS before RAS, and a CAS low state for more than 100 μs to enter a refresh mode, such as a self-refresh mode. There is.

[0006] Of these, self-refresh is a mode in which the DRAM itself refreshes at a fixed cycle. During this time, access is disabled, so that it is used for system standby or the like.

The RAS only refresh only needs to select a word line (performed by a Row address), and does not need to input a Column address. CA
Since the S-before-RAS refresh uses a refresh address counter inside the DRAM, no input of a Row address is required, but a refresh address cannot be freely selected unlike the RAS only refresh.

When data is read from the DRAM, R
An ow address is designated, the corresponding data is once read out from the memory cell to the sense amplifier, amplified, and only the data of the designated Column address is output to the outside. At the same time, the data read and amplified by the sense amplifier is written back to the memory cell again. When writing data to a DRAM, a row address is designated and the corresponding data is temporarily read from a memory cell to a sense amplifier, amplified, and further replaced with data externally input only to a designated column address. Is written back into the memory cell together with the data.

On the other hand, the refresh operation is performed before data is lost from the capacitor of each memory cell of the DRAM.
This data is once read out to the sense amplifier, amplified, and written back again. That is, refreshing is exactly the same operation as data reading and writing except for data rewriting and output.

For this reason, in the case of a system in which all Row addresses are accessed within a certain period of time, such as when it is used as an image memory, refresh is not always necessary and may be omitted. FIG. 6 shows a timing chart of DRAM data access and RAS only refresh.

[0011]

Since refresh is a process of repeating charging and discharging of word lines and bit lines, the longer the refresh cycle, the lower the power consumption. Further, in order to prevent a decrease in the bandwidth of the DRAM (data transfer capability per fixed time), it is desirable to omit the refresh if possible. There is a problem that refresh cannot be omitted.

It is an object of the present invention to provide a method in which all Ro
Even if the system does not access the w address,
An object of the present invention is to provide a memory control device that prevents unnecessary power consumption and bandwidth reduction due to excessive refresh by excluding addresses accessed within a predetermined time when refreshing a memory.

[0013]

In order to solve the above-mentioned problems, in the memory control device of the present invention, a refresh counter for counting a cycle shorter than a refresh cycle specified in a DRAM and an address accessed within a predetermined time are provided. It has an address storage circuit for storing, and refresh is performed excluding the address.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a memory control device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a memory control device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a memory control circuit, which includes a timing control circuit 2, an address generation circuit 3, a refresh counter 4, and a row address storage circuit 5. The timing control circuit 2 has D
RAM control signal RAS (Row Address St)
probe), CAS (Column Address)
(Strobe) and WE (Write Enable).

The address generation circuit 3 generates a write address, a read address, and a refresh address for the DRAM. The refresh counter 4 is tREF which is の of the refresh period tREF specified by the DRAM.
/ 2 is counted. The row address storage circuit 5 includes an address decoder 6 and a flag register 7, and sets and stores flags of all row addresses accessed within a predetermined time.

When data access is not being performed, the timing control circuit 2 performs intensive refresh once every two times of the timing signal of tREF / 2 cycle output from the refresh counter 4. That is, the refresh cycle is tREF. The refresh address is generated by the address generation circuit 3.

Here, if data access is not performed during tREF / 2 immediately before the concentrated refresh is performed, the concentrated refresh is performed once every two times. FIG. 2A shows a timing chart.

T immediately before the concentrated refresh is performed
When data access is performed during REF / 2, Ro
The w address storage circuit 5 sets and flags all the Row addresses. When performing the concentrated refresh, the timing control circuit 2 performs the refresh except for the refresh of the Row address, and performs only the refresh of the Row address after tREF / 2. here,
If data access is performed again during tREF / 2, refresh is not performed.

As a result, the number of times of refresh can be reduced, and the time tREF ′ from the time of data access until the next refresh is performed satisfies tREF or less. Thereafter, the refresh is performed in the tREF cycle until the data access of the Row address is performed. As described above, when data access of a certain Row address is performed, when that Row address is subsequently refreshed, it is refreshed at a different timing from other refreshes, but the tREF cycle is always maintained. FIG. 2B shows a timing chart.

Note that the row address storage circuit 5 of the above embodiment comprises an address decoder 6 and a flag register 7, and all the R addresses accessed within a certain period of time.
The ow address flag is set and stored.
Needless to say, the row address storage circuit 5 may store the row address itself. Further, the cycle of the refresh counter 4 is set to a refresh cycle tR specified by the DRAM.
Although an example in the case of と し た of EF has been described, the cycle of the refresh counter 4 may be any value as long as it is equal to or less than tREF. Further, in the above embodiment, data access is 1
Although the example of the number of times has been described, any number of data accesses may be performed.

In the first embodiment of the present invention having the above-described configuration, when performing the concentrated refresh of the memory, the addresses accessed within a predetermined time are excluded, so that unnecessary power consumption due to excessive refresh is reduced. Bandwidth can be prevented from lowering.

FIG. 3 is a block diagram showing a memory control device according to a second embodiment of the present invention. In FIG. 3, reference numeral 8 denotes a memory control circuit, which comprises a timing control circuit 9, an address generation circuit 3, a refresh counter 10, and a Row address storage circuit 5. The timing control circuit 9 controls the DRAM based on the DRAM control signals RAS, CAS, and WE.
Control. The address generation circuit 3 generates a write address, a read address, and a refresh address for the DRAM. Refresh counter 10 is DRA
M prescribed distributed refresh cycle tREF / 512 1 /
2 (tREF / 512) / 2 is counted.
The row address storage circuit 5 sets and stores flags of all row addresses accessed within a predetermined time.

When data access is not being performed, the timing control circuit 9 performs distributed refreshing once every two times of the (tREF / 512) / 2 cycle timing signal output from the refresh counter 10. That is, the cycle of the distributed refresh is tREF / 512, and the cycle of the refresh in each Row address unit is tREF / 512.
REF. The refresh address is generated by the address generation circuit 3.

Here, if data access is not performed during tREF / 2 immediately before the refresh of each Row address is performed, the distributed refresh is performed as it is once every two times. FIG. 4A shows a timing chart.

TRE immediately before the refresh is performed
When data access is performed during F / 2, the row address storage circuit 5 sets a flag of the row address and stores the flag. When performing the distributed refresh, the timing control circuit 9 performs the refresh except for the refresh of the Row address, and performs only the refresh of the Row address after tREF / 2. Here, tREF / 2
If the data is accessed again during this time, no refresh is performed.

As a result, the number of times of refresh can be reduced, and the time tREF ′ from data access to the next refresh can satisfy tREF or less. Thereafter, the refresh is performed in the tREF cycle until the data access of the Row address is performed. As described above, when data access of a certain Row address is performed, when the Row address is refreshed thereafter, the refresh is performed at a timing different from that of the previous refresh, but the tREF cycle is always maintained. FIG. 4B shows a timing chart.

The row address storage circuit 5 of the above embodiment is composed of an address decoder 6 and a flag register 7, and all the R addresses accessed within a certain time are used.
The ow address flag is set and stored.
Needless to say, the row address storage circuit 5 may store the row address itself. Further, the cycle of the refresh counter 10 is set to a refresh cycle t specified by the DRAM.
Although an example in which 1/2 of REF is set to 1/2 is shown, the cycle of the refresh counter 10 is tREF /
Any value may be used as long as it is 512 or less. Further, in the embodiment, the example in which the data access is performed once is shown, but the data access may be performed any number of times.

In the second embodiment of the present invention having the above-described configuration, when performing distributed refresh of a memory, an address accessed within a predetermined time is excluded, so that unnecessary power consumption due to excessive refresh can be reduced. Bandwidth can be prevented from lowering.

In each of the above embodiments, the memory is a DRAM.
Has been described as an example, but the present invention is not limited to the above embodiments, and can be implemented in various modifications without departing from the gist of the invention.

[0031]

According to the present invention, the following effects can be obtained by the configuration described above.

By excluding addresses accessed within a certain period of time when refreshing the memory, it is possible to prevent unnecessary power consumption and bandwidth reduction due to excessive refresh.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory control circuit according to a first embodiment.

FIG. 2 is a diagram showing a timing chart of the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a memory control circuit according to a second embodiment.

FIG. 4 is a diagram showing a timing chart of the second embodiment.

FIG. 5 is a diagram showing a timing chart of a conventional refresh method.

FIG. 6 is a diagram showing a timing chart of data access and refresh of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory control circuit, 2 ... Timing control circuit, 3 ... Address generation circuit, 4 ... Refresh counter, 5 ... Ro
w address storage circuit, 6 ... address decoder, 7 ... flag register.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5B024 AA01 AA09 BA21 BA29 DA10 DA14

Claims (4)

[Claims] 1. A memory control device for controlling data input / output to / from a memory, comprising: a refresh counter for counting a cycle shorter than a refresh cycle specified for the memory; an address generating circuit for generating a refresh address; A memory control device, comprising: an address storage circuit that stores an executed address; and performing refresh while excluding an address for which data input / output has been performed within a predetermined time. 2. The memory control device according to claim 1, wherein the address storage circuit comprises an address decoder and a flag register, and stores a flag of an address at which data input / output has been performed. 3. The memory control device according to claim 1, wherein the refresh is performed by a centralized refresh method. 4. The memory control device according to claim 1, wherein the refresh is performed by a distributed refresh method.