JPH01224994A - Refreshing device for dynamic ram - Google Patents

Abstract

PURPOSE:To improve the execution efficiency of a microcomputer by providing a second refreshing pulse to refresh a dynamic RAM when a control signal, which does not exclusively possess a bus, is outputted while execution processing is executed to the microcomputer. CONSTITUTION:When the control signal, which does not exclusively possess a bus 2, is not outputted from a microcomputer 1, a dynamic RAM 3 is refreshed at a refreshing circuit 4 for every constant time at a clock counter circuit 5. When the control signal is outputted, the dynamic RAM 3 is refreshed at a second refreshing circuit 8 based on the control signal. Namely, during a refreshing period by the second refreshing pulse, the execution of the microcomputer 1 is not stopped. Thus, the execution efficiency of the microcomputer 1 using the dynamic RAM 3 can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a refresh device for rewriting the contents of a dynamic RAM used as a storage device of a microcomputer.
More specifically, the present invention relates to a refresh device that can perform refresh without stopping the execution process of a microcomputer.

[Conventional Examples] In recent years, with the development of electronic technology, various microcomputers have been developed, and many products and systems using these microcomputers have been proposed. Furthermore, various types of memories with lower power consumption and larger capacities have been proposed as memory devices for microcomputers. among them.

In particular, large-capacity dynamic RAM stores information using electric charges stored in the capacitor, so that information is lost over time, so it is refreshed at regular cycles.
In other words, it is necessary to rewrite the contents.

Therefore, as shown in Figure 3, dynamic RAM
A microcomputer device using a refresh device is equipped with a refresh device.

In the figure, a dynamic RAM 3 connected to a microcomputer 1 via a bus 2 is refreshed by a refresh pulse from a refresh circuit 4. The refresh pulse is obtained at the timing of a signal output when the clock/counter circuit 5 counts a certain period of time T according to an instruction from the microcomputer 1 (FIG. 4(a)). Further, the refresh circuit 4 outputs a signal to the WAIT circuit 6 to cause the microcomputer 1 to wait (stop execution) during the refresh period. As a result, the CPU clock is no longer output from the WAIT circuit 6, the operation of the microcomputer 1 is stopped, and the dynamic RAM 3 is refreshed (see FIGS. 4(a) and 4(b)).

[Problems to be Solved by the Invention] By the way, the above-mentioned dynamic RAMI refresh is performed regardless of the execution processing content of the microcomputer 1.
This is done every fixed time T. Therefore, the microcomputer 1 has the drawback that the execution processing time is necessarily shortened by the refresh period, and the execution efficiency is low.

This invention was made in view of the above-mentioned drawbacks by noting that a microcomputer has a control signal that does not require exclusive use of the bus during execution processing, for example, an AVMA signal in the case of a Motorola 6809E microcomputer. and its purpose is dynamic RAM
An object of the present invention is to provide a refresh device that can improve the execution efficiency of a microcomputer using a microcomputer.

[Means for Solving the Problems] In order to achieve the above object, the refresh device of the present invention connects a dynamic RAM connected to a microcomputer via a bus to a clock/counter circuit according to instructions from the microcomputer. This is a refresh device that refreshes with a refresh pulse output from a refresh circuit when a certain period of time has been counted, and this control signal is set by the control signal output from the microcomputer during execution processing that does not monopolize the bus. a flip-flop circuit,
A second refresh pulse that outputs a second refresh pulse for rewriting the contents of the dynamic RAM when this flip-flop circuit is set, and a logic between this second refresh pulse and the refresh pulse. A first logic circuit that calculates the sum is provided.

Further, in the refresh device, the refresh circuit and the second refresh circuit output a reset signal for resetting the clock counter circuit at the output timing of the refresh pulse and the second refresh pulse, and the reset signal A second logic circuit is provided for calculating the logical sum of .

[Function] In the above configuration, if the microcomputer does not output a control signal that does not monopolize the bus, the clock/counter circuit outputs the
The dynamic RAM is refreshed by the refresh circuit. When the control signal is output, the dynamic RAM is refreshed by the second refresh circuit based on the control signal. That is, the execution of the microcomputer is not stopped during the refresh period by the second refresh pulse. Further, the dynamic RAM is refreshed by either the refresh pulse output from the refresh circuit or the second refresh pulse output from the second refresh circuit.

At this time, the clock counter circuit is reset by the refresh pulse or the second refresh pulse. That is, when the control signal is output, the interval between refresh pulses output from the refresh circuit becomes longer than the predetermined time.

[Example] Hereinafter, an example of the present invention will be described based on the drawings. In FIG. 1, the same parts as in FIG. 3 are designated by the same reference numerals, and redundant explanation will be omitted.

In FIG. 1, when the microcomputer 1 is a Motorola 6809H LSI, the microcomputer 1 is equipped with an AVMA terminal. That A
The AVMA signal from the VMA terminal is input to the D set input terminal of the flip-flop circuit 7, and the CPU clock is input to the CK clock input terminal of this flip-flop circuit 7. That is, the flip-flop circuit 7 outputs a signal in which the AVMA signal is synchronized with the CPU clock timing (hereinafter referred to as a VMA equivalent signal), and the second refresh circuit 8 is activated by this VMA equivalent signal. Ru. As a result, the second refresh pulse is output from the second refresh circuit 8 while the VAN equivalent signal is output. This second refresh pulse is input to one input terminal of the first logic circuit (2-OR circuit) 9, and the other input terminal receives a refresh pulse (hereinafter referred to as the first refresh pulse) from the refresh circuit 4. pulse) is input. The first or second refresh pulse that has been logically summed by the first logic circuit 9 is input to the dynamic RAM 3. Further, in order to reset the clock counter circuit 5, the refresh circuit 4 outputs a first reset signal, the second refresh circuit 8 outputs a second reset signal, and the first reset signal is output from the second refresh circuit 8.
A second reset signal is input to the second logic circuit (2-OR circuit) 10. The first or second reset signal that has been logically summed by the second logic circuit IO is input to the reset terminal of the clock counter circuit 5.

Next, the operation of the refresh device having the above configuration will be explained based on the time chart of FIG. 2.

First, it is assumed that a certain period of time T is counted by the clock counter circuit 5 according to an instruction from the microcomputer 1, and a signal is outputted from the clock counter circuit 5 to activate the refresh circuit 4 every certain period of time T. . That is, as shown in FIG. 4(a), as in the conventional case, an L level signal is input to the refresh circuit 4 at fixed time intervals T, and during the L level period, the refresh circuit 4
A first refresh pulse is input to the dynamic RAM 3 via the logic circuit 9.

Here, when the execution process of outputting the AVMA signal (see (C) in the figure) from the AVMA terminal is performed in the microcomputer 1, the flip-flop circuit 7 outputs the AVM signal from the AVMA terminal.
It is set by the A signal at the timing of the CPU clock, and is reset at the timing of the next CPU clock. During this period (refresh period), the flip-flop circuit 7 outputs a VMA equivalent signal (for example, an L level signal: see (d) in the same), and the second refresh circuit 8 outputs a second refresh pulse. . This second
The refresh pulse is input to the dynamic RAM 3 via the first logic circuit 9, thereby refreshing the dynamic RAM 3.

That is, as shown in FIGS. 2(a) and 2(d), the dynamic RAM 3 is refreshed within a certain period of time T, and the clock counter circuit 5 is reset, so that refreshment is performed after the certain period of time T. is not performed (see the dashed line in FIG. 3A), in that case, the clock counter circuit 5 is reset at the timing of the second refresh pulse, and then counting of the above-mentioned fixed time T is started. Also, the refresh period, WA
Since the CPU clock is continuously output from the IT circuit 6, the execution processing of the microcomputer 1 is not stopped.

In this way, refresh of dynamic RAM3 is
When the above AVMA signal is output and the clock
This is performed when the counter circuit 5 has counted a certain period of time T. That is, during the execution process of the microcomputer 1, the dynamic RAM 3 can be refreshed when the above-mentioned AVMA signal that does not exclusively use the bus 2 is output, and the execution process of the microcomputer 1 does not have to be in a standby (execution stop) state. Therefore, the execution efficiency of the microcomputer 1 can be increased.

[Effects of the Invention] As explained above, according to the present invention, when a control signal that does not occupy a bus is output during execution processing by a microcomputer, a second refresh pulse is provided to refresh the dynamic RAM. Therefore, it is not necessary to stop the execution of the microcomputer during the refresh period of the dynamic RAM, and therefore the execution efficiency of the microcomputer can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a refresh device showing an embodiment of the present invention, FIG. 2 is a time chart diagram for explaining the operation of the refresh circuit, and FIG. 3 is a schematic block diagram of a conventional refresh device. 4 are time charts for explaining the operation of the conventional refresh device. In the figure, 1 is a microcomputer (6809E), 2
is a bus, 3 is a dynamic RAM, 4 is a refresh circuit, 5 is a clock/counter circuit, 6 is a WAIT circuit, 7 is a flip-flop circuit, 8 is a second refresh pulse, and 9 is a first logic circuit ( 2 OR circuit), 10
is the second logic circuit (2-OR circuit).

Claims (2)

[Claims] (1) Refreshing that refreshes the dynamic RAM connected to the microcomputer via a bus with a refresh pulse output from the refresh circuit when a certain period of time is counted by the clock/counter circuit according to instructions from the microcomputer. In the apparatus, a flip-flop circuit to which the control signal is set by the control signal output from the microcomputer during execution processing that does not exclusively occupy the bus; and when the flip-flop circuit is set, the control signal is set in the dynamic RAM. a second refresh pulse that outputs a second refresh pulse for rewriting the contents of the second refresh pulse; and a first logic circuit that calculates the logical sum of the second refresh pulse and the refresh pulse; The dynamic R is activated by the refresh pulse or the second refresh pulse output from the circuit.
A refresh device characterized by refreshing an AM. (2) The clock signal is output from the refresh circuit and the second refresh circuit at the output timing of the refresh pulse and the second refresh pulse.
A reset signal is output to reset the counter circuit,
2. The refresh device according to claim 1, further comprising a second logic circuit that calculates the logical sum of the reset signals.