KR0176464B1 - Reflash control circuit of dram - Google Patents

Abstract

The present invention discloses a refresh control circuit of a dynamic random access memory device. The circuit is configured to determine priority of write and refresh operations of a memory by inputting the write flag storage means for storing the write flag, the refresh flag storage means for storing the refresh flag, and the write flag and the refresh flag. Inputting a first output signal of the priority determining means to generate a write execution flag and inputting a second output signal of the priority determining means to generate a refresh execution flag and determining the priority Refresh execution flag generating means for inputting to the means, the write execution flag signal and the refresh execution signal are input to generate a memory control signal for controlling the memory, the write execution flag storage means, the refresh execution flag storage means Memory generating signal for controlling And a storage means for inputting data from the outside into the dynamic random access memory device when the output signal of the write flag storage means is in the second state. Therefore, the refresh control of the memory can be effectively performed.

Description

Refresh Control Circuit of Dynamic Random Access Memory Device

1 is a block diagram of a refresh control circuit of the dynamic random access memory device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory device (DRAM), and more particularly to a refresh control circuit of a dynamic random access memory device.

A problem in controlling the dynamic random access memory device by a personal computer (PC) is asynchronousness of the personal computer and the controller of the dynamic random access memory device. The personal computer operates asynchronously with the control of the dynamic random access memory device and the dynamic random access memory device controller periodically refreshes the dynamic random access memory device. Therefore, a case where two operations occur at the same time occurs. However, due to the structure of the dynamic random access memory device, two operations cannot be performed at the same time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a refresh control circuit of a dynamic random access memory device capable of minimizing interference caused by the refresh of the dynamic random access memory device during processing and external write operations when two operations occur simultaneously. It is.

A refresh control circuit of the dynamic random access memory device of the present invention for achieving the above object comprises: flag storage means for storing a write flag and a refresh flag; Priority determining means for inputting the write flag and refresh flag to determine priorities of write and refresh operations of a memory; Write execution flag generating means for inputting a first output signal of said priority determining means to generate a write execution flag and input to said priority determining means; Refresh execution flag generating means for inputting a second output signal of said priority determining means to generate a refresh execution flag and inputting into said priority determining means; A memory control signal for generating the memory control signal for controlling the memory by inputting the write execution flag signal and the refresh execution flag signal and generating a signal for controlling the write execution flag storage means and the refresh execution flag storage means; Signal generating means; Storage means for inputting data from the outside into the memory when the output signal of the write flag storage means is in the second state, wherein the priority determining means comprises the write flag storage means and the refresh flag storage means; The method may determine whether to perform the write control or the refresh control on the basis of the output states of the write execution flag storage means and the refresh flag storage means.

The refresh method and circuit of the dynamic random access memory device of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a refresh circuit of the dynamic random access memory device of the present invention.

In FIG. 1, the write flag storing means 10, the refresh period counting means 20, the refresh flag storing means 30, the priority determining means 40, the write execution flag storing means 50, and the reclaiming means. The flash execution flag storing means 60, the DRAM control signal generating means 70, and the storing means 80 are constituted.

The operation of the configuration is as follows.

The refresh period counting means 20 having a time corresponding to the refresh cycle of the DRAM as one cycle outputs a pulse through the signal ib each time the cycle is reached. The signal ib means that it is time to refresh. The refresh flag storing means 30 is set by the signal ib.

The signal ia is a signal corresponding to a write enable signal applied from the outside, and the write flag storage means 10 is set by the signal ia.

The storage means 80 transfers the signal ih to the signal oh by setting the signal oa. That is, external data is temporarily stored in the storage means 80.

The priority determining means 40 sets one of the signals id, ie by the signals oa, ob and od, oe. The signal id sets the write execution flag storage means 50 and the signal ie sets the refresh flag storage means 60, respectively.

The DRAM control signal generation means 70 performs write control on the DRAM when the signal od is set, and the refresh control of the DRAM via the signal of when the signal oe is set. After the DRAM refresh control is performed, the refresh flag storage means 30 and the refresh execution storage means 60 are reset through a signal of. After the DRAM write control is performed, the write flag storage means 10 and the refresh flag storage means 30 are reset through a signal ofd.

The refresh cycle counting means 20 checks the refresh cycle and activates the signal ib every one cycle. The signal ia represents a write enable signal applied from the outside, the signal ih is connected to a data bus applied externally, and the signal oh is connected to a data bus of the DRAM. The signal of is a DRAM control signal and includes an address, an output enable, a write enable, a RAS, and a CAS signal.

The circuit performs the following five operations.

In the case of the operations (1) and (2), the circuit performs the write or refresh control by the signals ia and ib in the wait state. In other words, in this case, only one operation is requested when no operation is performed.

In the case of the operations 4 and 5, one of the signals od and oe is set, and thus the standby operation by the signals ia and ib is performed after the corresponding operation is finished. That is, when one operation is already executed and another operation is requested to be executed.

In the case of operation (3), a request for two executions is simultaneously applied. In this case, one operation having a high priority based on the priority is executed first, and then another operation is executed. In other words, when no operation is executed, the execution of both operations is required at the same time.

If the operation of the priority determining means 400 is represented by a truth table as follows.

(1) When light control has high priority

(2) When Ripple Number Control is High Priority

The third state of the truth table, i.e., the state indicated by *, is a state for determining priority. When the states of the signals (oa, ob, od, oe) input to the priority determining means 40 are set, set, reset, reset, respectively, and the states of the output signals id, ie are set, reset, respectively. This is the case where the refresh control priority is high when the write control has a high priority and the states of the output signals id and ie are reset and set, respectively.

Therefore, the refresh control circuit of the dynamic random access memory device of the present invention can efficiently perform the refresh control.

Claims (2)

Flag storage means for storing a write flag and a refresh flag; Priority determining means for determining a priority of a write and refresh operation of a memory by inputting the write flag and the refresh flag; Write execution flag generating means for inputting a first output signal of said priority determining means to generate a write execution flag and input to said priority determining means; Refresh execution flag generating means for inputting a second output signal of said priority determining means to generate a refresh execution flag and inputting into said priority determining means; A memory control signal for generating a memory control signal for controlling the memory by inputting the write execution flag signal and a refresh execution flag signal and generating a signal for controlling the write execution flag storage means and the refresh execution flag storage means; Signal generating means; Storage means for inputting data from the outside into the memory when the output signal of the write flag storage means is in the second state, wherein the priority determining means comprises the write flag storage means and the refresh flag storage means; Based on the output states of the write execution flag storage means and the refresh flag storage means, determining whether to perform the write control or the refresh control preferentially. Flash control circuit. 2. The method of claim 1, wherein the priority determining means comprises: outputting the respective output signals of the write flag storage means, the refresh flag storage means, the write execution flag storage means, and the refresh flag storage means, respectively; When the input signals are in the second state, the second state, the first state, the first state, the second state, and the first state, the light control is preferentially performed and the second state, the second state, the first state, and the first state. The refresh control circuit of the dynamic random access memory device according to claim 1, wherein the state, the first state, and the second state perform refresh control preferentially and determine priority.