JPH0420698U - - Google Patents
Info
- Publication number
- JPH0420698U JPH0420698U JP6235390U JP6235390U JPH0420698U JP H0420698 U JPH0420698 U JP H0420698U JP 6235390 U JP6235390 U JP 6235390U JP 6235390 U JP6235390 U JP 6235390U JP H0420698 U JPH0420698 U JP H0420698U
- Authority
- JP
- Japan
- Prior art keywords
- ram
- refresh
- refreshing
- cycle
- access means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Dram (AREA)
Description
第１図は本考案の基本的構成を示す図、第２図
はプログラムと処理データとをＤ−ＲＡＭに蓄積
させるコンピユータシステムのシステム回路図、
第３図は外部メモリからプログラムを読出してデ
ータ処理を実行する場合におけるＤ−ＲＡＭのリ
フレツシユ動作手順を示すフローチヤート、第４
図はアドレスバス、データバス、チツプセレクト
信号、リフレツシユ信号の出力タイミングの一例
を示すタイミングチヤートである。
１……第一のＤ−ＲＡＭ、２……第二のＤ−Ｒ
ＡＭ、３……アクセス手段、４……選択リフレツ
シユ手段、５……基本リフレツシユ手段、６……
データ加工手段。
FIG. 1 is a diagram showing the basic configuration of the present invention, and FIG. 2 is a system circuit diagram of a computer system that stores programs and processing data in a D-RAM.
FIG. 3 is a flowchart showing the D-RAM refresh operation procedure when reading a program from an external memory and executing data processing;
The figure is a timing chart showing an example of the output timing of the address bus, data bus, chip select signal, and refresh signal. 1...First D-RAM, 2...Second D-R
AM, 3...access means, 4...selective refresh means, 5...basic refresh means, 6...
Data processing means.
Claims (1)
せるコンピユータシステムにおいて、 プログラムを蓄積する第一のＤ−ＲＡＭと、 処理データを蓄積する第二のＤ−ＲＡＭと、 命令フエツチサイクルにおいては第一のＤ−Ｒ
ＡＭを、データのリード／ライトサイクルにおい
ては第二のＤ−ＲＡＭを選択的にアクセスするア
クセス手段と、 アクセス手段が第一のＤ−ＲＡＭをアクセス中
には第二のＤ−ＲＡＭを継続的にリフレツシユし
、アクセス手段が第二のＤ−ＲＡＭをアクセス中
には第一のＤ−ＲＡＭを継続的にリフレツシユす
る選択リフレツシユ手段と、 第一または／及び第二のＤ−ＲＡＭが選択リフ
レツシユ手段で所定時間内にリフレツシユされな
い場合に、第一または／及び第二のＤ−ＲＡＭに
対して基本リフレツシユサイクルでリフレツシユ
を行う基本リフレツシユ手段 とを具備したことを特徴とするＤ−ＲＡＭのリフ
レツシユ装置。[Scope of Claim for Utility Model Registration] A computer system that stores programs and processing data in a D-RAM, comprising a first D-RAM that stores programs, a second D-RAM that stores processing data, and an instruction memory. In the Tsuchi cycle, the first D-R
AM, access means selectively accesses the second D-RAM during a data read/write cycle, and continuously accesses the second D-RAM while the access means is accessing the first D-RAM. selective refresh means for refreshing the first D-RAM and continuously refreshing the first D-RAM while the access means is accessing the second D-RAM; A D-RAM refresh device comprising a basic refresh means for refreshing the first and/or second D-RAM in a basic refresh cycle when the D-RAM is not refreshed within a predetermined time. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6235390U JPH0420698U (en) | 1990-06-13 | 1990-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6235390U JPH0420698U (en) | 1990-06-13 | 1990-06-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420698U true JPH0420698U (en) | 1992-02-20 |
Family
ID=31591424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6235390U Pending JPH0420698U (en) | 1990-06-13 | 1990-06-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420698U (en) |
-
1990
- 1990-06-13 JP JP6235390U patent/JPH0420698U/ja active Pending
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