JPH0181794U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a memory device according to an embodiment of this invention, FIG. 2 is a timing diagram showing its write access operation, FIG. 3 is a block diagram showing a conventional memory device, and FIG. 4 is a block diagram showing its write access operation. FIG. 3 is a timing diagram showing an access operation. 1 is a memory device, 2 is a CPU, 12 is a memory element, 17 is a memory controller, and 18 is a data buffer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims for Utility Model Registration] (1) In a memory device that writes write data sent from the central processing unit to a memory element via a data buffer in accordance with a write access from the central processing unit, the central processing unit A memory device comprising: a memory controller that starts an internal write cycle and simultaneously returns a response signal to the central processing unit when a memory write request signal is detected in response to the write access from the central processing unit. (2) The memory device according to claim 1, wherein the data buffer has a function of latching write data from the central processing unit. (3) The memory device according to claim 1 or 2, wherein the memory controller has a function of inhibiting the next memory write request until the end of the internal write cycle. .