JPH0455650U

JPH0455650U -

Info

Publication number: JPH0455650U
Application number: JP9773190U
Authority: JP
Priority date: 1990-09-18
Filing date: 1990-09-18
Publication date: 1992-05-13

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図は第１図の実施例の書込み時の動作
を説明するためのタイミングチヤート、第３図は
第１図の実施例の読出し時の動作を説明するため
のタイミングチヤート、第４図は従来のメモリシ
ステムの構成を示すブロツク図、第５図は従来例
における読出し時のキヤツシユヒツト時の動作を
説明するためのタイミングチヤート、第６図は従
来例における読出し時のキヤツシユミスヒツト時
の動作を説明するためのタイミングチヤートであ
る。１……プロセツサ、２……ＤＭＡ制御回路（Ｄ
ＭＡＣ）、３……ＣＰＵバス、４……主記憶制御
回路（ＭＣ）、５……主記憶装置、６……メモリ
バス、７……キヤツシユ記憶。 FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the write operation of the embodiment of FIG. 1, and FIG. 3 is an embodiment of the embodiment of FIG. 1. 4 is a block diagram showing the configuration of a conventional memory system. FIG. 5 is a timing chart for explaining the cache operation during read in the conventional example. FIG. 6 is a timing chart for explaining the operation at the time of cache miss during read in the conventional example. 1... Processor, 2... DMA control circuit (D
MAC), 3...CPU bus, 4...Main memory control circuit (MC), 5...Main storage device, 6...Memory bus, 7...Cache storage.

Claims

[Claims for Utility Model Registration] A main storage device 5 and a cache storage device 7 are built in, and a bus
It has a processor 1 having a snoop function, one or more masters 2 that can access a main memory 5, and a main memory control circuit 4, and the processor 1, master 2, and main memory control circuit 4 are The main storage device 5 is connected to the main storage device 5 by a memory bus 6 independent from the CPU bus 3, and the master 2 is connected to the main storage device 5 by a CPU bus 3. When writing data to the cache memory device 7, the main memory control circuit 4 writes the data to the corresponding address in the main memory device 5, regardless of whether the write address exists on the cache memory device 7, and the master 2 writes the data to the corresponding address in the main memory device 5. When reading data from the main memory reading device 5, the main memory control circuit 4 reads data from the corresponding address in the main memory device 5, regardless of whether the read address exists on the cache memory device 7 or not. If the read address is latched and the read address exists on the cache storage device 7, the latched data is discarded, and if the read address does not exist on the cache storage device 7, the latched data is A memory control circuit, characterized in that the memory control circuit is configured to transfer the data to the CPU bus 3.