JPH01151341U

JPH01151341U -

Info

Publication number: JPH01151341U
Application number: JP4768488U
Authority: JP
Priority date: 1988-04-11
Filing date: 1988-04-11
Publication date: 1989-10-19

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例によるメモリチエ
ツク回路のブロツク図、第２図は従来のメモリチ
エツク回路のブロツク図である。１Ａ，１Ｂはラインバツフアメモリ、３は比較
器。なお図中、同一符号は同一、又は相当部分を
示す。 FIG. 1 is a block diagram of a memory check circuit according to an embodiment of this invention, and FIG. 2 is a block diagram of a conventional memory check circuit. 1A and 1B are line buffer memories, and 3 is a comparator. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

An independent line buffer memory for print data and a line buffer memory for data check that store print data in the same write address in a printer, etc. and read out the print data at the same read address when reading, and the above two line buffer memories. A memory check circuit equipped with a comparator that reads and compares print data at the same read address when reading from the file memory.