JPS6384647U - - Google Patents
Info
- Publication number
- JPS6384647U JPS6384647U JP17822186U JP17822186U JPS6384647U JP S6384647 U JPS6384647 U JP S6384647U JP 17822186 U JP17822186 U JP 17822186U JP 17822186 U JP17822186 U JP 17822186U JP S6384647 U JPS6384647 U JP S6384647U
- Authority
- JP
- Japan
- Prior art keywords
- read error
- error detection
- detection circuit
- main memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 10
- 230000001629 suppression Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案を実現する一実施例を示す図で
ある。
１…主記憶回路、２…主記憶データビツト部、
３…パリテイビツト部、４…パリテイチエツク回
路、５…パリテイエラー検出回路、６…パリテイ
エラー検出抑止回路、７…データライン、８…パ
リテイビツトライン、９…パリテイ検出ストロー
ブライン、１０…パリテイエラー検出ライン、１
１…パリテイチエツク出力ライン、１２…エラー
検出抑止ライン。
FIG. 1 is a diagram showing an embodiment of the present invention. 1... Main memory circuit, 2... Main memory data bit section,
3... Parity bit section, 4... Parity check circuit, 5... Parity error detection circuit, 6... Parity error detection suppression circuit, 7... Data line, 8... Parity bit line, 9... Parity detection strobe line, 10... Parity error detection line, 1
1... Parity check output line, 12... Error detection suppression line.
Claims (1)
ンピユータ用主記憶装置において、該読出し誤り
検出機能を有効にするか、無効にするかをハード
ウエアにより指定する手段により、該情報記憶回
路に読出し誤りが発生した場合に、上記読出し誤
り検出機能の有効／無効の指定に応じて、該読出
し誤りの検出／未検出を行なうことを特徴とする
主記憶装置の読出し誤り検出回路。 In a computer main memory device having a read error detection circuit for an information storage circuit, a read error occurs in the information storage circuit by means of specifying by hardware whether the read error detection function is enabled or disabled. A read error detection circuit for a main memory device, wherein the read error detection circuit detects/non-detects the read error in accordance with designation of enable/disable of the read error detection function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17822186U JPS6384647U (en) | 1986-11-21 | 1986-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17822186U JPS6384647U (en) | 1986-11-21 | 1986-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384647U true JPS6384647U (en) | 1988-06-03 |
Family
ID=31120154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17822186U Pending JPS6384647U (en) | 1986-11-21 | 1986-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384647U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009527820A (en) * | 2006-02-21 | 2009-07-30 | フリースケール セミコンダクター インコーポレイテッド | Error correction method and error correction apparatus |
-
1986
- 1986-11-21 JP JP17822186U patent/JPS6384647U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009527820A (en) * | 2006-02-21 | 2009-07-30 | フリースケール セミコンダクター インコーポレイテッド | Error correction method and error correction apparatus |
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