JPS6384648U - - Google Patents

Info

Publication number
JPS6384648U
JPS6384648U JP17913086U JP17913086U JPS6384648U JP S6384648 U JPS6384648 U JP S6384648U JP 17913086 U JP17913086 U JP 17913086U JP 17913086 U JP17913086 U JP 17913086U JP S6384648 U JPS6384648 U JP S6384648U
Authority
JP
Japan
Prior art keywords
data
memory section
memory
writing
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17913086U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17913086U priority Critical patent/JPS6384648U/ja
Publication of JPS6384648U publication Critical patent/JPS6384648U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す構成図である。 1…メモリ部、2…ホストプロセツサ、3…メ
モリプロセツサ、4…プロセツサバス。
FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Memory unit, 2...Host processor, 3...Memory processor, 4...Processor bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データを格納するためのメモリ部と、このメモ
リ部に対してデータの書き込み及び読み込みを行
うホストプロセツサと、前記メモリ部へのデータ
の書き込み時に当該データにもとずいてパリテイ
ビツト及び誤り検出訂正コードを作成してこれら
をデータと共に前記メモリ部に記憶させ、メモリ
部のデータの読み込み時に当該データ及びパリテ
イビツトにもとずきパリテイチエツクを行つてデ
ータの誤り検出を行うと共に、誤り検出時には誤
り検出訂正コードにもとずきデータの誤りを訂正
するメモリプロセツサとを備えてなることを特徴
とするメモリ装置。
A memory section for storing data, a host processor for writing and reading data into the memory section, and a parity bit and error detection and correction code based on the data when writing data to the memory section. These are created and stored in the memory section along with the data, and when reading the data in the memory section, a parity check is performed based on the data and the parity bit to detect errors in the data, and when an error is detected, the error detection is performed. 1. A memory device comprising: a memory processor that corrects data errors based on a correction code.
JP17913086U 1986-11-21 1986-11-21 Pending JPS6384648U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17913086U JPS6384648U (en) 1986-11-21 1986-11-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17913086U JPS6384648U (en) 1986-11-21 1986-11-21

Publications (1)

Publication Number Publication Date
JPS6384648U true JPS6384648U (en) 1988-06-03

Family

ID=31121915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17913086U Pending JPS6384648U (en) 1986-11-21 1986-11-21

Country Status (1)

Country Link
JP (1) JPS6384648U (en)

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