JPH0474340U - - Google Patents
Info
- Publication number
- JPH0474340U JPH0474340U JP11874990U JP11874990U JPH0474340U JP H0474340 U JPH0474340 U JP H0474340U JP 11874990 U JP11874990 U JP 11874990U JP 11874990 U JP11874990 U JP 11874990U JP H0474340 U JPH0474340 U JP H0474340U
- Authority
- JP
- Japan
- Prior art keywords
- memory section
- microprocessor
- check bit
- diagnostic
- operation mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Microcomputers (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図はＥＤＣ回路の一例を示すプ構成ブロ
ツク図である。
１……マイクロプロセツサ、２……メモリ部、
２１……データ格納領域、２２……パリテイチエ
ツクビツト格納領域、３……誤り検出・訂正回路
（ＥＤＣ回路）、４……ＥＤＣ制御回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of an EDC circuit. 1...Microprocessor, 2...Memory section,
21... Data storage area, 22... Parity check bit storage area, 3... Error detection/correction circuit (EDC circuit), 4... EDC control circuit.
Claims (1)
サによつてアクセスされ、データとパリテイチエ
ツクビツトとを記憶するＥＣＣ化構成のメモリ部
とを備えたマイクロプロセツサ装置であつて、 前記メモリ部への書き込みデータを入力しチエ
ツクビツトの作成を行うと共に、当該チエツクビ
ツトのメモリ部への書き込みと、前記メモリ部か
ら読み出されたデータとパリテイチエツクビツト
とを入力し誤りを検出する通常動作と、強制的に
エラーを発生するチエツクビツトとデータを読込
みそれに対する動作からその機能を診断する診断
動作を行う誤り検出・訂正回路と、 前記メモリ部へのアクセス動作と誤り検出・訂
正回路の診断モードとの動作モードを決める情報
をアドレス情報として出力する前記マイクロプロ
セツサ内に設けられた動作モード出力手段と、 アドレス情報をモニタしていて当該アドレス情
報に基づいて誤り検出・訂正回路に対して通常動
作と、診断動作のいずれかの動作を指示するＥＤ
Ｃ制御回路と を設けたことを特徴とするメモリ装置。[Claims for Utility Model Registration] A microprocessor device comprising a microprocessor and a memory section having an ECC structure that is accessed by the microprocessor and stores data and parity check bits. , Input write data to the memory section to create a check bit, write the check bit to the memory section, input data read from the memory section and a parity check bit, and detect errors. An error detection/correction circuit performs normal operation, a check bit that forcibly generates an error, a diagnostic operation for reading data and diagnosing its function from the operation thereon, and an error detection/correction circuit for accessing the memory section. an operation mode output means provided in the microprocessor that outputs information that determines the operation mode between the diagnostic mode and the operation mode as address information; ED that instructs either normal operation or diagnostic operation.
A memory device comprising: a C control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11874990U JPH0474340U (en) | 1990-11-13 | 1990-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11874990U JPH0474340U (en) | 1990-11-13 | 1990-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474340U true JPH0474340U (en) | 1992-06-29 |
Family
ID=31866703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11874990U Pending JPH0474340U (en) | 1990-11-13 | 1990-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474340U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694447A (en) * | 1979-12-27 | 1981-07-30 | Fujitsu Ltd | Test system of parity checker |
| JPS6426938A (en) * | 1987-07-23 | 1989-01-30 | Fujitsu Ltd | Test system for ras circuit |
| JPS6431538A (en) * | 1987-07-28 | 1989-02-01 | Topy Ind | Method and device for engaging outer cylinder with insert |
-
1990
- 1990-11-13 JP JP11874990U patent/JPH0474340U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694447A (en) * | 1979-12-27 | 1981-07-30 | Fujitsu Ltd | Test system of parity checker |
| JPS6426938A (en) * | 1987-07-23 | 1989-01-30 | Fujitsu Ltd | Test system for ras circuit |
| JPS6431538A (en) * | 1987-07-28 | 1989-02-01 | Topy Ind | Method and device for engaging outer cylinder with insert |
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