JPS6232813B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the improvement of information processing devices, and particularly to memory with error correction codes, even if the interface between the memory controller and the CPU is a parity check method, read data from the memory If there is an error in the data, it can be easily detected.

Conventionally, as shown in FIG. 1, in the write cycle of a memory device, a parity bit is generated and added to the write data in the main body, for example, a CPU 1, and the data and parity bit are written into the memory 3 by the memory controller 2 as they are. Also, in the read cycle, the read data and parity bits read from the memory 3 are sent to the CPU 1 via the memory controller 2.
A parity check was being carried out at In the above-mentioned conventional information processing device having the CPU 1-memory 3 interface, even if a parity error is detected, it is not possible to distinguish whether it is an error on the interface or an error in the memory element, and error isolation is required. There were difficulties.

In addition, when adding an error correction code method to improve reliability and error detection rate of the memory part while leaving the interface as is, for example, if check bits are generated and written from the data as is, even if a parity error occurs. However, the problem was that apparently correct data was written, and the error disappeared.

The object of the present invention has been made in view of the above-mentioned circumstances.Even if the interface between the memory controller and the CPU for the memory with an error correction code is a parity check method, it is possible to read data from the memory. To provide an information processing device that forms a parity bit so that if there is an error in read data, it can be easily detected.

The details of the present invention will be explained below with reference to the drawings. FIG. 2 shows a basic circuit of one embodiment thereof, in which 5 is a main body, for example, a CPU, 6 is a memory controller, and 7 is a memory portion. and CPU
5 and memory controller 6 is a parity check interface.
The interface between the memory 7 and the memory 7 is an error correction type interface. The memory controller 6 has an error correction function, generates a check bit from the write data from the CPU 6 and the parity bit, and writes it into the memory 7. For example, when an error is detected from the write data and parity bit, an uncorrectable error code is written to the memory 7. Therefore, the memory 7 is a memory with an error correction code. The interface signals shown in the figure include only data, parity bits, and check bits.
Other signals such as addresses are omitted because they are not relevant to the present invention.

FIG. 3 shows details of the portion of the above memory controller according to the present invention. 11 is an error check/correction circuit, 12 is a parity generator, 13 is a parity bit converter, 14 is read data (data and check bits) from the memory, 15 is output data via the circuit 11, and 16 is a parity generator 12. 17 is the uncorrectable error signal from the error check and correction circuit, 18 is the parity bit after conversion, and this parity bit 1
8 and the above output data 15 are the memory controller 6.
This is an interface signal between the CPU 5 and the CPU 5.

The operation of the information processing apparatus of the present invention configured as described above will be explained.

Since the interface between the CPU 5 and the memory controller 6 is of a parity check type, a parity bit is generated from the read data by the parity generator 12. At this time, the read data is checked by the error check/correction circuit 11, and if there is no error or a single error, the correct parity bit is sent from the parity generator 12 via the parity bit converter 13.
Send to CPU5. However, if an uncorrectable error is detected in the error check/correction circuit 11, an uncorrectable error signal is output to the parity bit converter 13. When the converter 13 detects an uncorrectable error signal 17, it converts the parity bit 16 from the parity generator 12 into an incorrect parity bit.
Send to CPU5. If the parity bit 18 for the output data 15 is transferred to the CPU 5 as described above, when the CPU 5 performs a parity check, if an uncorrectable error occurs, it can be detected as a parity error.

As is clear from the above description, according to the present invention, even if the interface between the memory controller 6 and the CPU 5 uses a parity check method different from that of the interface between the memory 7 and the memory controller 6, the read from the memory 7 The parity bit allows the CPU 5 to be notified that there is an error in the data. Therefore, there is no need for a special error notification function, and the memory controller 6 and
It has the advantage of being able to form an interface between the CPUs 5. In the above embodiment, parity bits are exchanged for uncorrectable errors, but the same effect can be obtained by converting output data and generating parity errors in the CPU.

[Brief explanation of the drawing]

1 and 2 are basic circuit diagrams of the conventional information processing apparatus and the present invention, and FIG. 3 is a detailed circuit diagram of a portion of the memory control shown in FIG. 2 according to the present invention. 11...Error check/correction circuit,
12... Parity generator, 13... Parity bit converter, 14... Read data, 15... Output data, 17... Uncorrectable error signal,
18... Parity bit signal.

Claims (1)

[Claims] 1 A memory with an error correction code, an error check/correction circuit that detects an uncorrectable error from read data read from the memory and outputs an error signal, a parity generator that generates parity bits from the read data, and the above-mentioned amplifier. An information processing device comprising: a conversion circuit that converts the parity bit into a parity bit that becomes an uncorrectable error when a correctable error signal is generated.