JPH01145732A - Parity bit generating system - Google Patents

Abstract

PURPOSE:To curtail the data output time and to operate the storage device at a high speed by providing a logical value inverting circuit so that an error correction time by a parity bit generating circuit is absorbed in an error correction time of an error correcting circuit. CONSTITUTION:A parity bit generating circuit 16 receives a data dr read out of a storage circuit 14, and generates a parity bit pr to the data dr. A logical value inverting circuit 100 receives the parity bit pr generated by the parity bit generating circuit 16, and a correction executing signal ec for showing whether an error correcting circuit 15 performed an error correction to the data dr or not, and when it is shown that the correction executing signal ec has performed the error correction, a logical value of the parity bit pr is inverted, and outputted as a correction parity bit pc. In such a way, an error correction time by the parity bit generating circuit is absorbed in the error correction time, a data output time is curtailed and a storage device can be operated at a high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a parity bit generation method in a storage device that performs error correction on data read from a storage circuit, adds a parity bit, and outputs the data, the data output time of the storage device is minimized. A storage circuit that stores data with an error correction code, and a memory circuit that receives the data with an error correction code read from the storage circuit, performs one-bit error correction on the data, and outputs it as corrected data. a parity bit generation circuit that receives data read from the storage circuit and generates a parity bit for the data; a parity bit generated by the parity bit generation circuit; and an error correction circuit. receives a correction execution signal indicating whether or not error correction has been performed on the data, and when the correct execution signal indicates that error correction has been performed, inverts the logic value of the parity bit and corrects the correction parity bit. The configuration is such that a logical value inverting circuit is provided to output the output as follows.

[Industrial Field of Application] The present invention relates to a storage device, and more particularly to a parity bit generation method in a storage device that performs error correction on data read from a storage circuit, adds a parity bit, and outputs the data.

For example, in electronic exchanges, etc., data transmitted from a central control unit etc. via a data bus is written, and in a storage device that transmits read data to a central control unit etc. via a data bus, data is written. There is also a possibility that an error may occur during data transmission over a data bus during reading and during storage in a storage circuit, and countermeasures are taken depending on the probability of error occurrence.

In the present invention, a parity bit is added to the data transmitted on the data bus so that a single bit error can be detected, and an error correction code is added to the data written to the memory circuit to correct a single bit error. The target is a storage device that is capable of detecting two-bit errors.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional storage device of this type, and FIG. 5 is a diagram illustrating the data output time in FIG. 4.

4 and 5, a write address aw is input to the storage device l via the address/control bus 2, and a write address aw generated based on the odd parity rule, for example, is input via the data bus 3. Paritipi I-p. When the write data dw to which p is added is input, the parity check circuit (PC) 12 checks the input write parity bit p. The write data dw with the tag is checked for errors based on the odd parity rule, and a write error detection signal eW indicating the check result is transmitted to the storage control circuit (MC) 11.

On the other hand, the error correction code generation circuit (ECCG) 13 receives the input write data d. For this, a write error correction code cw that can correct a - bit error and detect a 2-bit error is generated and input to the error code storage section (C) 142 of the memory circuit (MEM) 14.

Note that write data dw is input to the data storage unit CD) 141 of the storage circuit 14.

When the write error detection signal ew transmitted from the parity check circuit 12 is set to an error detection state (for example, logic "1"), the storage control circuit 11 controls the storage circuit 14.
A response signal m indicating error detection is sent to the address/control bus 2 without performing write control on the write error detection signal e. is set to an error-free state (for example, logic "O"), the write address a8 is input to the memory circuit 14, and the input write data d1 is transferred to the data storage section 141, and the write error is detected. The correction code c is respectively written into the entertainment code storage unit 142.

Next, when the read address a1 is input to the storage device 1 via the address/control bus 2, the storage control circuit 1
1 inputs the input read address a7 to the memory circuit 14, reads the continuous data d1 from the corresponding read address a of the data storage section 141, and also reads the continuous data d1 from the corresponding read address a of the error code storage section 142. The error correction code C1 is successively generated and transmitted to an error correction circuit (ECC) 15.

The error correction circuit 15 performs a predetermined error check on the transmitted read data d and the read error correction code c, .
Based on the correction rule, the presence or absence of a two-bit error is detected and a read error detection signal e1 indicating the inspection result is sent to the storage control circuit 11.
In addition to transmitting the information to the - bit error location,
If detected, correct the error location (logical value inversion)
The corrected data dc is generated and outputted to the data bus 3 as well as transmitted to the parity bit generation circuit (PC) 16.

The parity bit generation circuit 16 generates a correction parity bit pc based on the odd parity check rule for the transmitted correction data dc, and outputs it to the data bus 3 together with the correction data dc output by the error correction circuit 15.

Note that the error correction circuit 15 detects a two-bit error in the read data d, and outputs a read error detection signal e.

When set to an error detection state (for example, logic "1"), the storage control circuit 11 outputs a response signal m indicating error detection to the address/control bus 2, and corrects the corrected data output to the data bus 3. Notify that dc is invalid.

As shown in FIG. 5, after the read address a is input to the storage device 1 and the read time t1 has elapsed, the read data d1 and the read error correction code C, , are successively output from the memory circuit 14 as shown in FIG. and then error correction time 1
After the elapse of t, the error correction circuit 15 outputs the corrected data dc, and further after the elapse of the parity bit generation time t, the parity bit generation circuit 16 outputs the corrected parity bit pc.
will be output.

[Problem to be Solved by the Invention 1] As is clear from the above description, in a conventional storage device, after the read address a is input from the address/control bus 2, the correction parity bit p is input to the data bus 3.
The data output time until the correction data dc with c is outputted is < (t, +tz +t+) as shown in FIG. 5, which poses a problem that hinders the speeding up of the storage device.

The present invention aims to shorten the data output time of a storage device as much as possible.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 14 is data d with error correction code cr.
A storage circuit 15 for storing data r receives the data dr with error correction code C1 read from the storage circuit 14, performs -bit error correction on the data d, and stores the corrected data d.
This is an error correction circuit that outputs as c.

16 is a parity bit generation circuit provided according to the present invention.

100 is a logic value inversion circuit provided according to the present invention.

[Effect]

Parity bit generation circuit 16 receives data d read from storage circuit 14 and generates parity bit pr for data d1.

The logic value inversion circuit 100 includes a parity bit generation circuit 16
The parity bit pr generated by , the logical value of the parity bit Pr is inverted and output as a corrected parity bit pc.

Therefore, the elapsed time from when data and error correction codes are read from the storage circuit until corrected data with corrected parity bits is output from the storage device is determined mostly by the error correction time of the error correction circuit, and The error correction time by the circuit is absorbed by the error correction time, the data output time is reduced, and the speed of the storage device is promoted.

〔Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a storage device according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating the data output time in FIG. 2. Note that the same reference numerals refer to the same objects throughout the plan.

In FIG. 2, the logical value inversion circuit 10 in FIG.
0, an exclusive OR circuit 17 is provided.

In FIGS. 2 and 3, a write address a is written to the storage device 1 via an address/control bus 2. is input, and when write data dw with a write parity bit P generated based on the odd parity rule is input via the data bus 3, the parity is changed in the same process as in FIG. The check circuit (PC) 12 writes parity bit p. Write data with d. The presence or absence of an error is checked based on the odd parity rule, and if no error is detected, an error correction code generation circuit (E
The write error correction code C8 generated by the CCG) 13, the write data d input from the data bus 3, and the error code storage section (C) 142 and data storage section (D) 141 of the memory circuit (MEM) 14. are written to the corresponding write address a, respectively.

In this state, when a read address a is input to the storage device l via the address/control bus 2, the memory control circuit (MC) 11 reads the input read address a,
is input to the storage circuit 14, and the data storage section (D) 1
The read data d is sequentially output from the corresponding read address a of 41 and transmitted to the error correction circuit (ECC) 15 and the parity bit generation circuit (PC) 16, and the corresponding read data d of the error code storage unit (C) 14-2 is sequentially transmitted to the error correction circuit (ECC) 15 and the parity bit generation circuit (PC) 16. The error correction code C1 is successively read out from the read address a and transmitted to the error correction circuit 15.

The error correction circuit 15 detects the presence or absence of a two-bit error on the transmitted read data dr and read error correction code Cr based on a predetermined error check/correction agent, and outputs a read error detection signal er indicating the test result. is transmitted to the storage control circuit 11, and the location where the - bit error occurs is checked, and if detected, the error location is corrected (logical value inverted) to generate corrected data dc, which is output to the data bus 3. do.

Note that when the error correction circuit 15 does not perform any error correction on the read data d read from the data storage section 141 and outputs it as the still-corrected data dc, the error correction circuit 15 sets the correction execution signal ec to logic "0". Exclusive OR circuit 1 by setting
7 and read data d read from the data storage section 141 is subjected to -bit error correction and output as corrected data dc, the correction execution signal e
. is set to logic "1°" and transmitted to the exclusive OR circuit 17.

Parity bit generation circuit 16 generates read parity bit pr for read data d read from data storage section 141 based on the odd parity check rule, and transmits it to exclusive OR circuit 17 .

The exclusive OR circuit 17 executes exclusive OR processing on the correction execution signal ec transmitted from the error correction circuit 15 and the read parity bit pr transmitted from the parity bit generation circuit 16, and converts the execution result into a corrected parity. It is output to the data bus 3 as bit T)c.

That is, when the correction execution signal ec transmitted from the error correction circuit 15 is set to logic "0°", the exclusive OR circuit 17 selects the logic of the read parity bit Pr transmitted from the parity bit generation circuit 16. without inverting the value,
However, when the correction execution signal ec transmitted from the error correction circuit 15 is set to logic "1", the read parity transmitted from the parity bit generation circuit 16 is output as the side correction parity bit pc. The logical value of bit p1 is inverted and output as a corrected parity bit pc.

Therefore, the data d read from the data storage section 141,
is output to the data bus 3 as the corrected parity bit Pc without being corrected, the read data d
The read parity bit pr generated from , is outputted to the data bus 3 as the correction parity bit p,
Moreover, the data d read from the data storage section 141 is -
When the bit is corrected (logical value inversion) and output to the data bus 3 as a corrected parity bit pc, the read parity bit pr generated from the read data d is
Since the logical value of the corrected parity bit pc is inverted and outputted to the data bus 3 as the corrected parity bit pc, the corrected parity bit pc always becomes an accurate parity bit with respect to the corrected data dc.

As shown in FIG. 3, after the read address a is input to the storage device 1 and the read time tl has elapsed, the read data d and the read error correction code C1 are read out from the storage circuit 14, as shown in FIG. After the error correction circuit 1
5 outputs the correction data de and the correction execution signal ec after the error correction time t2 has elapsed, and in parallel, the parity bit generation circuit 16 outputs the correction data de and the correction execution signal ec after the error correction time t2 has elapsed.
After the lapse of time, the read parity bit p1 will be output.

The normal parity bit generation time t is the error correction time t2
Since it is a short time compared to , the read parity bit p is output before the correction data dc is output, and when the correction execution signal ec is output from the error correction circuit 15, the logical value inversion time t4 has elapsed. It will be output later as a corrected parity bit pc.

Note that since the logical value inversion time t4 is a time that can be ignored with respect to the error correction time t2 or the parity bit generation time t, the data output time in FIG. 3 is approximately (t++t
2), and compared to the data output time in FIG. 5, the parity bit generation time is reduced by approximately t3.

As is clear from the above description, according to this embodiment, the parity bit generation circuit 16 immediately generates the read parity bit p for the read data dr read from the data storage section 141, and the error correction circuit 15 Since the corrected parity bit Pc is set by manipulating the logical value depending on whether or not to perform -bit error correction on the read data d1,
The data output time is reduced by the parity bit generation time t3 compared to the conventional case.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the parity check circuit 12 and the parity bit generation circuit 16 are not limited to those based on the odd parity rule, but are based on even parity rules. (Although this is also considered, the effect of the present invention does not change even in such a case.

〔Effect of the invention〕

As described above, according to the present invention, in the storage device, the elapsed time from when data and error correction codes are successively outputted from the storage circuit to when corrected data with corrected parity bits is outputted from the storage device is almost the same as when the error correction circuit The error correction time by the parity bit generation circuit is absorbed by the error correction time, reducing the data output time and promoting higher speed of the storage device.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing a storage device according to an embodiment of the invention, Fig. 3 is a diagram illustrating the data output time in Fig. 2, and Fig. 4 is a diagram illustrating the conventional method. FIG. 5 is a diagram illustrating an example of a certain storage device, and is a diagram illustrating the data output time in FIG. 4. In the figure, 1 is a storage device, 2 is an address/control bus,
3 is a data bus, 11 is a memory control circuit (MC), 12 is a parity check circuit (PC), 13 is an error correction code generation circuit (ECCG), 14 is a memory circuit (MEM), 15
16 is an error correction circuit (ECC), 16 is a parity bit generation circuit (PC), 17 is an exclusive OR circuit, 100 is a logical value inversion circuit, 141 is a data storage unit (CD), 142 is an error code 7P-Ray 6th month Principle of C mouth 1 mouth! n (Kengachi August (two words Otsu'ki l (next day))
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Claims (1)

[Claims] A memory circuit (14) for storing data (d_r) with an error correction code (c_r), and a data (d_r) with the error correction code (c_r) read from the memory circuit (14).
an error correction circuit (15) that receives -bit error correction on the data (d_r) and outputs it as corrected data (d_c), the storage device comprising: data (d_r)
a parity bit generation circuit (16) that receives the data (d_r) and generates a parity bit (p_r) for the data (d_r).
and a correction execution indicating whether or not the parity bit (p_r) generated by the parity bit generation circuit (16) and the error correction circuit (15) have performed error correction on the data (d_r). signal (e_c), and when the correction execution signal (e_c) indicates that error correction has been performed,
A parity bit generation method, comprising: a logic value inversion circuit (100) that inverts the logic value of the parity bit (p_r) and outputs it as a corrected parity bit (p_c).