JPH0371236A - Error detecting system - Google Patents

Abstract

PURPOSE:To detect the error of a memory and the runaway of a computer by adding respectively different error detecting codes to an operation code and operands and providing an error detecting circuit. CONSTITUTION:Respectively different error detecting codes are added to the operation code and the operands and the error detecting circuit 3 collates a signal for discriminating the operation code from the operands outputted from the computer 1 with data including an error detecting code read out from a memory 2 to detect the error of the memory 2 and the runaway of the computer 1. Namely, the memory error disabling the correct reading of data from the memory 2 and the computer runaway disabling the program counter in the computer 1 to noncorrectly indicate addresses are detected. Consequently, the error of the memory 2 and the runaway of the computer 1 can be detected only by adding the small number of bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error detection system, and more particularly to an error detection system for detecting memory errors and computer runaways.

[Prior Art] Conventionally, as a technique for detecting errors in computers, for example, Japanese Patent Laid-Open No. 56-31143 discloses a technique for detecting errors in data in order to identify whether or not data read from memory is an operation code. It is shown that a runaway prevention bit is added. Further, Japanese Patent Application Laid-Open No. 57-98047 discloses an error code detection function using redundant bits in the instruction code for detecting code errors.

[Problems to be Solved by the Invention] However, in the former (Japanese Unexamined Patent Publication No. 56-31143), as the number of runaway prevention bits increases,
In the latter method (Japanese Unexamined Patent Publication No. 57-98047M), memory errors can be detected, but computer runaway cannot be detected.

An object of the present invention is to provide an error detection system that can detect memory errors and computer runaways by simply adding a small number of bits.

[Means for Solving the Problems] The present invention adds different error detection codes to operation codes and operands, and the error detection circuit uses a signal that distinguishes between the operation code and the operands output from the computer and a signal read from the memory. The gist of the present invention is an error detection system that detects memory errors and computer runaways by comparing data containing the error detection code that has been detected.

[Operation] Different error detection codes are added to the operation code and the operand, and the error detection circuit detects the signal that distinguishes the operation code and operand from the computer and the data containing the error detection code read from the memory. This is used to detect memory errors and computer runaways. That is, it detects memory errors in which data cannot be read correctly from memory, and computer runaways in which the computer's program counter does not indicate correct addresses.

[Example] An example embodying the present invention will be described below with reference to the drawings.

In the system of this embodiment, the central processing unit (hereinafter referred to as
A parity detection circuit 3 as an error detection circuit is provided for a CPU 1 and a memory 2, and these are connected via a bus 4. Since this bus 4 transmits parity bits for detecting errors, it is one bit wider than the bit width of a normal data bus. IF (I n5truct
ion F-etch) signal 5 is the parity detection circuit 3
is input.

This IF signal 5 becomes "1" during the operation code fetch cycle, and becomes rOJ during the operand fetch cycle.

The parity detection circuit 3 sends an interrupt signal (hereinafter referred to as INT signal) 6 to the CPU' to indicate that an error has been detected.
Output to l. This INT signal @6 becomes rOJ when there is no error, and becomes "1" when there is an error.

Also, a parity bit is added to the operation code so that the parity of all data including the parity bit is odd parity, and a parity is added to the operand so that the parity of all data including the parity bit is even parity. Bits are added. And C.P.
U1 sequentially reads out operation codes and operands from memory 2 and proceeds with processing.

Next, error detection when fetching an operation code will be explained. The parity detection circuit 3 inputs the data including the parity bit read from the memory 2 and the signal 5 (=1) indicating the operation code fetch cycle output from the CPU 1. If all the parities of the signal are even, it is determined that there is no error, and the INT signal 6 is set to rOJ.The parity detection circuit 3 also detects the data read out from the memory 2 and the data read out from the memory 2. For example, it is determined that there is an error and the INT signal 6 is set to "1".

The CPU 1 inputs this INT signal 6, which is "1", and
Start exception handling. Incidentally, at this time, the CPU 1 may be reset.

Next, error detection during operand fetching will be explained. The parity detection circuit 3 receives data including a parity bit and an IF signal @5 (=0) indicating an operand fetch cycle output from the CPU 1. As a result, the parity detection circuit 3 determines that there is no error if all the parities of these signals are even, and sets the INT signal 6 to "O". Furthermore, if all the parities of these signals are odd, the parity detection circuit 3 determines that there is an error, and changes the INT signal 6 to "
1".

Now, to explain the specific occurrence of an error, first consider the case where a 1-bit error occurs when reading data from the memory 2. In the case of an error in the memory 2 (when data cannot be read correctly from the memory 2), the parity detection circuit 3 detects odd parity as described above, and an error is detected.

Next, consider a case where the CPU 1 goes out of control and the program counter in CPLJi goes out of control.

In this case, it is not always the case that the correct operation code address is output when fetching the operation code, and the correct operand address is not necessarily output when fetching the operand. Therefore, an operand is read when an operation code is fetched, and an operation code is read when an operand is fetched.

When the CPU 1 runs out of control (when the CPU program counter does not indicate the correct address), the parity detection circuit 3 inputs the data including the parity bit read from the memory 2 and the IF signal @5 output from the CPU. ,
If all the parities of these signals are odd parity, the CPU
1 out of control is detected.

In this way, according to this embodiment, different parity information (error detection code) is used between the operation code and the operand.
is added, and the parity detection circuit (error detection circuit)
An error in the memory 2 and a runaway in the CPU 1 are detected by comparing the IF signal 5 outputted from the Lll to distinguish between an operation code and an operand with data including parity pits read from the memory 2. In other words, memory 2 cannot read data correctly from memory 2.
It is possible to detect errors in the CPU and runaway of the CPU in which the program counter of the CPU does not indicate the correct address. As a result, conventionally, JP-A-56-3114
In JP-A-57-98047, computer runaway could not be detected, but in this embodiment, 1 bit of parity information is added to the data. At the same time, by simply adding some hardware (parity detection circuit 3), errors in the memory 2 and runaway of the CPU 1 can be detected.

Note that this invention is not limited to the above embodiments,
For example, an error detection/correction code such as a Hamming code or a Fire code may be used as the error detection code.

[Effects of the Invention] As described in detail above, according to the present invention, an excellent effect is achieved in that memory errors and computer runaways can be detected simply by adding a small number of bits.

[Brief explanation of drawings]

The figure is an overall system diagram for explaining the embodiment. 1 is a CPU, 2 is a memory 1, and 3 is a parity detection circuit as an error detection circuit.

Claims (1)

[Claims] 1. Adding different error detection codes to the operation code and the operand, and causing the error detection circuit to output a signal output from the computer to distinguish between the operation code and the operand, and data containing the error detection code read from the memory. An error detection system that detects memory errors and computer runaways by comparing them.