JPS54129948A - Data processor - Google Patents

Data processor

Info

Publication number
JPS54129948A
JPS54129948A JP3826178A JP3826178A JPS54129948A JP S54129948 A JPS54129948 A JP S54129948A JP 3826178 A JP3826178 A JP 3826178A JP 3826178 A JP3826178 A JP 3826178A JP S54129948 A JPS54129948 A JP S54129948A
Authority
JP
Japan
Prior art keywords
word
parity
instruction
signal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3826178A
Other languages
Japanese (ja)
Inventor
Hideo Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3826178A priority Critical patent/JPS54129948A/en
Publication of JPS54129948A publication Critical patent/JPS54129948A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To make it possible to prevent the execution of an improper instruction, by providing methods of discriminating, checking and detecting whether write or read information is an instruction word or data word.
CONSTITUTION: During a write from CPU1 to memory unit 2, signals of "0" for an instruction word and "1" for a data word are transmitted as the 1st control signals to parity-bit generating method 12 via the 1st sending method 11. In method 12, parity bits are added to the instruction word and data word by the 1st control signal with the both opposite in parity, and then stored in memory unit 2. At the time of a read from unit 2, parity-checking method 14 outputs to improper-word detecting method 15 a signal of "0" when the parity of the read word is odd and a signal of "1" when even. Method 15 detects an improper word by the signal from method 14, and the 2nd control singal from the 2nd sending method 13 indicating that the instruction word is "1" and the data word is "0", and if it is found, the read of words to CPU1 is stopped via gate control method 16.
COPYRIGHT: (C)1979,JPO&Japio
JP3826178A 1978-03-31 1978-03-31 Data processor Pending JPS54129948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3826178A JPS54129948A (en) 1978-03-31 1978-03-31 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3826178A JPS54129948A (en) 1978-03-31 1978-03-31 Data processor

Publications (1)

Publication Number Publication Date
JPS54129948A true JPS54129948A (en) 1979-10-08

Family

ID=12520368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3826178A Pending JPS54129948A (en) 1978-03-31 1978-03-31 Data processor

Country Status (1)

Country Link
JP (1) JPS54129948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371236A (en) * 1989-08-10 1991-03-27 Nippondenso Co Ltd Error detecting system
JPH0962525A (en) * 1995-08-30 1997-03-07 Nec Ic Microcomput Syst Ltd Device and method for detecting program runaway

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371236A (en) * 1989-08-10 1991-03-27 Nippondenso Co Ltd Error detecting system
JPH0962525A (en) * 1995-08-30 1997-03-07 Nec Ic Microcomput Syst Ltd Device and method for detecting program runaway

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